Semiconductor & Computer Engineering
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Difference between revisions of "amd/am186/n80c186-25"
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Latest revision as of 15:17, 13 December 2017
| Edit Values | |
| N80C186-25 | |
| General Info | |
| Manufacturer | AMD |
| Model Number | N80C186-25 |
| Part Number | N80C186-25 |
| Market | Embedded |
| General Specs | |
| Family | Am186 |
| Series | Am186 |
| Frequency | 25 MHz |
| Bus speed | 6.25 MHz |
| Bus rate | 6.25 MT/s |
| Microarchitecture | |
| Microarchitecture | 80186 |
| Core Name | 80186 |
| Technology | CMOS |
| Word Size | 16 bit |
| Cores | 1 |
| Max Memory | 1 MiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 1 W |
| Vcore | 5 V ± 10 % |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
N80C186-25 is an 80186-based microprocessor manufactured by AMD. This model is a redesigned CMOS version that operated at 25 MHz and introduced a number of enhancements in addition to being lower-power CMOS, including a DRAM Refresh Control Unit and various power saving modes.
Contents
Cache[edit]
- Main article: 80186 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
| L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- 10 new instructions
- Two DMA channels
- Three programmable interrupt timers
- Local Bus Controller
- Object code-compatible with all 86/88 software
- Power saving mode
- DRAM Refresh Control Unit
Documents[edit]
- AMD 80C186 (June 1994), Publication #17907 Rev B
