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| first announced = October 10, 2006 | | first announced = October 10, 2006 | ||
| first launched = December, 2006 | | first launched = December, 2006 | ||
− | | production start = | + | | production start = |
− | | production end = | + | | production end = |
| arch = Many-core 32-bit microprocessor | | arch = Many-core 32-bit microprocessor | ||
| isa = | | isa = | ||
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| tech = CMOS | | tech = CMOS | ||
| clock min = 1 MHz | | clock min = 1 MHz | ||
− | | clock max = | + | | clock max = 333 Mhz |
| package = FCBGA-868 | | package = FCBGA-868 | ||
| package 2 = FCBGA-896 | | package 2 = FCBGA-896 | ||
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{{table count|col=5|ask=[[Category:microprocessor models by ambric]][[instance of::microprocessor]][[microprocessor family::Am2000]]}} | {{table count|col=5|ask=[[Category:microprocessor models by ambric]][[instance of::microprocessor]][[microprocessor family::Am2000]]}} | ||
</table> | </table> | ||
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== Architecture == | == Architecture == | ||
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=== Communication === | === Communication === | ||
[[File:ambric neighbor channels.png|thumb|right|350px|'''Neighbor Channels''']] | [[File:ambric neighbor channels.png|thumb|right|350px|'''Neighbor Channels''']] | ||
− | Ambric's architecture makes heavy use of | + | Ambric's architecture makes heavy use of channels - synchronized interconnects that carry both data and instructions in a [[FIFO]]. Channels are a strong point of this architecture as all data goes through channels including [[memory]] and [[registers]]. Channel interconnects can be loosely divided into three categories: |
− | * '''Intra-Bric Channels''': internal channels that span no loner than a single bric. All basic communication utilizes these channels. They are dynamically configured by the instructions themselves. | + | * '''Intra-Bric Channels''': internal channels that span no loner than a single bric. All basic communication utilizes these channels. They are dynamically configured by the instructions themselves. Typical ALU [[register]]/[[memory]] utilizes these channels. |
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− | * '''Inter-Bric Channels''': also known as distanced bric channels, are communication channels that operate globally between any two brics. Switches are located at each of the control units (CUs). Routes are configured | + | * '''Inter-Bric Channels''': also known as distanced bric channels, are communication channels that operate globally between any two brics. Switches are located at each of the control units (CUs). Routes are configured |
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{{clear}} | {{clear}} | ||
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=== Brics === | === Brics === | ||
[[File:ambric bric.png|left]] | [[File:ambric bric.png|left]] | ||
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* 2x '''RAM Units''' (RU) | * 2x '''RAM Units''' (RU) | ||
− | ::Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel operating in FIFO and random access modes via the RU engines | + | ::Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel operating in FIFO and random access modes via the RU engines. |
{{clear}} | {{clear}} | ||
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==== SR Processor ==== | ==== SR Processor ==== | ||
[[File:ambric sr core instruction.png|right]] | [[File:ambric sr core instruction.png|right]] | ||
− | The '''SR''' ('''Streaming [[RISC]]''') Processor is a {{arch|32}} processor for fast simple operations | + | The '''SR''' ('''Streaming [[RISC]]''') Processor is a {{arch|32}} processor for fast simple operations. This processor can handle complex [[addressing]], [[serialization]] and [[deserialization]]. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes: |
* 1x ALU - 1x {{arch|32}} OR 2x {{arch|16}} operations | * 1x ALU - 1x {{arch|32}} OR 2x {{arch|16}} operations | ||
* 8x [[general-purpose registers|General Purpose]] [[register|Registers]] | * 8x [[general-purpose registers|General Purpose]] [[register|Registers]] | ||
* {{arch|16}} instruction word size | * {{arch|16}} instruction word size | ||
+ | * 3-stage channel datapath | ||
* 64 word local code/data RAM | * 64 word local code/data RAM | ||
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==== SRD Processor ==== | ==== SRD Processor ==== | ||
[[File:ambric srd core instruction.png|right]] | [[File:ambric srd core instruction.png|right]] | ||
− | The '''SRD''' ('''Streaming [[RISC]] with [[DSP]] extensions''') Processor is a {{arch|32}} processor for more complex operations that may benefit from [[instruction-level parallelism]] and iterative algorithms | + | The '''SRD''' ('''Streaming [[RISC]] with [[DSP]] extensions''') Processor is a {{arch|32}} processor for more complex operations that may benefit from [[instruction-level parallelism]] and iterative algorithms. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes: |
* 3x ALU | * 3x ALU | ||
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== Programming == | == Programming == | ||
− | + | {{empty section}} | |
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== Applications == | == Applications == | ||
The Am2000 has been used for high-definition video processing, medical imaging devices, high performance network processing, image recognition, and various military applications such as drones. | The Am2000 has been used for high-definition video processing, medical imaging devices, high performance network processing, image recognition, and various military applications such as drones. | ||
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== See also == | == See also == | ||
* [[massively parallel processor array]] | * [[massively parallel processor array]] | ||
* {{rapport|Kilocore}} | * {{rapport|Kilocore}} |
Facts about "Am2000 - Ambric"
designer | Ambric + |
first announced | October 10, 2006 + |
first launched | December 2006 + |
full page name | ambric/am2000 + |
instance of | microprocessor family + |
main designer | Ambric + |
manufacturer | TSMC + |
name | Ambric Am2000 + |
package | FCBGA-868 + and FCBGA-896 + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |