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[[File:arm2 block diagram.svg|750px]] | [[File:arm2 block diagram.svg|750px]] | ||
+ | == Core == | ||
== Core == | == Core == | ||
The ARM2 largely builds on the successful {{\\|ARM1}} design, featuring an extremely simple 32-bit single-chip [[RISC]] microprocessor implementation with a number of [[CISC]] features. The largest change to the pipeline is the augmentation of a new [[Booth's multiplier]] that was needed to support the new hardware multiplication instructions. | The ARM2 largely builds on the successful {{\\|ARM1}} design, featuring an extremely simple 32-bit single-chip [[RISC]] microprocessor implementation with a number of [[CISC]] features. The largest change to the pipeline is the augmentation of a new [[Booth's multiplier]] that was needed to support the new hardware multiplication instructions. | ||
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<div style="float: left; margin: 10px;">'''Register-Immediate:'''<br>[[File:arm1 reg imm.svg|300px]]</div></div> | <div style="float: left; margin: 10px;">'''Register-Immediate:'''<br>[[File:arm1 reg imm.svg|300px]]</div></div> | ||
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===== Multiplication ===== | ===== Multiplication ===== | ||
− | + | The ARM1 major performance issue was with multiplication. The ARM1 lacked hardware multiplication which meant software had to resort to a software-based solution (e.g., classic [[Shift-and-Add Multiplication]]). For example to perform <code>var = x * 5;</code> one could rewrite it as <code>var = x + (x << 2);</code> to achieve the same result without a multiplication operation. While originally was not thought to be a big program, software multiplication proved to be a rather serious bottleneck. | |
− | The ARM1 major performance issue was with multiplication. The ARM1 lacked hardware multiplication which meant software had to resort to a software-based solution (e.g., classic [[Shift-and-Add Multiplication]]). For example to perform <code>var = x * 5;</code> one could rewrite it as <code>var = x + (x << 2);</code> to achieve the same result without a multiplication operation. While originally was not thought to be a big | ||
This was addressed with the ARM2 which introduced a [[Booth's Multiplier]]. Conceptually, the multiplier sits on the "B" operand of the ALU in a similar way to how the barrel shifter sits on the "A" operand of the ALU, however there are some major differences in how they are implemented and operate. | This was addressed with the ARM2 which introduced a [[Booth's Multiplier]]. Conceptually, the multiplier sits on the "B" operand of the ALU in a similar way to how the barrel shifter sits on the "A" operand of the ALU, however there are some major differences in how they are implemented and operate. | ||
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{{clear}} | {{clear}} | ||
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===== Interrupt ===== | ===== Interrupt ===== | ||
The ARM2 has fast interrupt capabilities for real-time responses. Exceptions can occur internally or externally to the chip. The average interrupt latency is sub-2 µs with a worst case of sub-6 µs. An interrupt must wait for the currently executing instruction to complete before the interrupt executes. The current instruction completes only when a new instruction starts fetching. When an exception takes place, the processor sets the [[PC]] to a specific memory address within the [[interrupt vector table]]. | The ARM2 has fast interrupt capabilities for real-time responses. Exceptions can occur internally or externally to the chip. The average interrupt latency is sub-2 µs with a worst case of sub-6 µs. An interrupt must wait for the currently executing instruction to complete before the interrupt executes. The current instruction completes only when a new instruction starts fetching. When an exception takes place, the processor sets the [[PC]] to a specific memory address within the [[interrupt vector table]]. |
Facts about "ARM2 - Microarchitectures - Acorn"
codename | ARM2 + |
core count | 1 + |
designer | Acorn Computers + |
first launched | 1986 + |
full page name | acorn/microarchitectures/arm2 + |
instance of | microarchitecture + |
instruction set architecture | ARMv2 + |
manufacturer | VLSI Technology + and Sanyo + |
microarchitecture type | CPU + |
name | ARM2 + |
pipeline stages | 3 + |
process | 2,000 nm (2 μm, 0.002 mm) + |