Semiconductor & Computer Engineering
From WikiChip
Editing WikiChip talk:chip feed
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page is not enabled for semantic in-text annotations due to namespace restrictions. Details about how to enable the namespace can be found on the configuration help page.
| Latest revision | Your text | ||
| Line 1: | Line 1: | ||
| − | {{talk | + | {{title|WikiChip's Chip Feed}}<span style="float: right;">__TOC__</span> |
| + | |||
| + | == Welcome == | ||
| + | Welcome to Wikichip's Chip Feed! | ||
| + | |||
| + | Anything chip-related goes! | ||
| + | |||
| + | * Manufacturer News | ||
| + | * Designer News | ||
| + | * Technology News | ||
| + | * Roadmap Updates | ||
| + | * New Chips announcements | ||
| + | * New Architectures | ||
| + | * etc.. | ||
| + | |||
| + | |||
| + | [{{fullurl:{{TALKPAGENAMEE}}|action=edit§ion=new}} Click here to start a new topic.] | ||
| + | |||
| + | |||
| + | |||
| + | Trying to find your way? check [[WikiChip:welcome]]. | ||
| + | <hr> | ||
| + | = Discussion= | ||
| + | |||
| + | == Oracle's out the chip design business == | ||
| + | |||
| + | Over a week ago [https://twitter.com/WikiChip/status/903640505581494273 we've tweeted] the news that Oracle will be leaving the chip design business, at least for [[SPARC]]. Our source is someone in the know that we trust. Unfortunately Oracle has done this very quietly and without making any formal press statements. | ||
| + | |||
| + | This changed this week when on September 5th Oracle published an updated roadmap. The roadmap can be viewed here: http://www.oracle.com/us/products/servers-storage/servers/sparc/oracle-sparc/sparc-roadmap-slide-2076743.pdf | ||
| + | |||
| + | Take a note to the major change: | ||
| + | |||
| + | <gallery mode="nolines" heights="500px" widths="500px"> | ||
| + | File:oracle roadmap (jan 2017).png|Roadmap (January, 2017) | ||
| + | File:oracle roadmap (sept 2017).png|Roadmap (September, 2017) | ||
| + | </gallery> | ||
| + | |||
| + | Their roadmap pretty much confirms they've dropped future SPARC development. --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 17:34, 9 September 2017 (EDT) | ||
| + | |||
| + | : http://www.mercurynews.com/2017/09/05/oracle-slashes-more-than-900-santa-clara-jobs-more-worldwide/ | ||
| + | |||
| + | : 983 jobs were being cut in Santa Clara. --[[User:David|David]] ([[User talk:David|talk]]) 10:43, 13 September 2017 (EDT) | ||
| + | |||
| + | :: [[Oracle M8]] is finally announced https://www.oracle.com/corporate/pressrelease/oracle-sparc-m8-091817.html --[[User:David|David]] ([[User talk:David|talk]]) 10:04, 19 September 2017 (EDT) | ||
| + | |||
| + | == Apple A11 Bionic == | ||
| + | |||
| + | Apple just announced their "{{apple|A11|A11 Bionic}}" processor which will be used in an iPhone 8 and 8 Plus. 6 cores (2 big, 4 little), 64-bit, 4.3B xtors. The event can be watched here: https://www.apple.com/apple-events/september-2017/. --[[User:Inject|Inject]] ([[User talk:Inject|talk]]) 18:45, 12 September 2017 (EDT) | ||
| + | |||
| + | :The two extra little cores is just for marketing. "Hey we have 70% more multi-thread performance". I guess all the Android octa/deca-core marketing bullshit managed to get the best of them. --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 21:57, 12 September 2017 (EDT) | ||
| + | |||
| + | :: Lots of marketing talk throughout the keynote. "600 GOPS" for the NPU how do we even compare that to anything? What does a "3 core GPU design" even mean? what do "cores" mean in this context anyway? those area clearly not shaders or alike. It's all so ambiguous. Then we have the actual Monsoon and Mistral architectures that we know nothing about. I guess we'll need to get an actual iphone and run our own code to reverse engineer everything. --[[User:David|David]] ([[User talk:David|talk]]) 22:16, 12 September 2017 (EDT) | ||
| + | |||
| + | == Imagination Technologies == | ||
| + | |||
| + | Imagination introduced the [[PowerVR]] Series 9XE and 9XM + a new "PowerVR 2NX NNA" (NNA=Neural Network Accelerator). --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 00:54, 23 September 2017 (EDT) | ||
| + | |||
| + | == NDA broken/lifted, Coffee Lake announced early == | ||
| + | |||
| + | Since someone can't follow an embargo and leaked the slide deck early, Intel decided to announce {{intel|Coffee Lake|l=arch}} early. For the most part, we've had all the info already since the leaks happened to be spot-on so we've already had that info listed anyway. If you have anything to add, feel free to head to the {{intel|Coffee Lake|l=arch}} article. --[[User:David|David]] ([[User talk:David|talk]]) 12:23, 26 September 2017 (EDT) | ||
| + | |||
| + | == U54-MC Coreplex IP == | ||
| + | |||
| + | SiFive Launches First RISC-V Based CPU Core with Linux Support | ||
| + | |||
| + | "Inventors of RISC-V Unveil U54-MC Coreplex IP, a 64-Bit Multicore CPU Designed for Embedded Applications that Require a Full Operating System" | ||
| + | |||
| + | * https://www.sifive.com/posts/2017/10/04/sifive-launches-first-risc-v-based-cpu-core-with-linux-support/ | ||
| + | |||
| + | --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 23:01, 9 October 2017 (EDT) | ||
| + | |||
| + | == NXP announce their new flagship SoC - LX2160A == | ||
| + | |||
| + | * {{nxp|LX2160A}} - http://media.nxp.com/phoenix.zhtml?c=254228&p=irol-newsArticle&ID=2304668 | ||
| + | |||
| + | --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 14:10, 21 October 2017 (EDT) | ||
