Semiconductor & Computer Engineering
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Difference between revisions of "Template:x86 features"
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<tr style="vertical-align:top;"><td> | <tr style="vertical-align:top;"><td> | ||
<table class="tl1" style="font-size: 0.9em; float: left;"><!-- | <table class="tl1" style="font-size: 0.9em; float: left;"><!-- | ||
| − | -->{{#if: {{istrue|{{{mmx|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{mmx|}}}}} | <tr><th style="width: 100px;">MMX</th><td>MMX Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{emmx|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{emmx|}}}}} | <tr><th style="width: 100px;">EMMX</th><td>Extended MMX Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{3dnow|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{3dnow|}}}}} | <tr><th style="width: 100px;">3DNow!</th><td>3DNow! Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{e3dnow|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{e3dnow|}}}}} | <tr><th style="width: 100px;">E3DNow!</th><td>Extended 3DNow! Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse|}}}}} | <tr><th style="width: 100px;">SSE</th><td>Streaming SIMD Extensions</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse2|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse2|}}}}} | <tr><th style="width: 100px;">SSE2</th><td>Streaming SIMD Extensions 2</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse3|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse3|}}}}} | <tr><th style="width: 100px;">SSE3</th><td>Streaming SIMD Extensions 3</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{ssse3|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{ssse3|}}}}} | <tr><th style="width: 100px;">SSSE3</th><td>Supplemental SSE3</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse41|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse41|}}}}} | <tr><th style="width: 100px;">SSE4.1</th><td>Streaming SIMD Extensions 4.1</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: 100px;">SSE4.2</th><td>Streaming SIMD Extensions 4.2</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: 100px;">SSE4a</th><td>Streaming SIMD Extensions A</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: 100px;">AVX</th><td>Advanced Vector Extensions</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: 100px;">AVX2</th><td>Advanced Vector Extensions 2</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{avx512|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{avx512|}}}}} | <tr><th style="width: 100px;">AVX-512</th><td>Advanced Vector 512-bit</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: 100px;">ABM</th><td>Advanced Bit Manipulation</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: 100px;">TBM</th><td>Trailing Bit Manipulation</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{bmi1|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{bmi1|}}}}} | <tr><th style="width: 100px;">BMI1</th><td>Bit Manipulation Instruction Set 1</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{bmi2|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{bmi2|}}}}} | <tr><th style="width: 100px;">BMI2</th><td>Bit Manipulation Instruction Set 2</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{fma3|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{fma3|}}}}} | <tr><th style="width: 100px;">FMA3</th><td>3-Operand Fused-Multiply-Add</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{fma4|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{fma4|}}}}} | <tr><th style="width: 100px;">FMA4</th><td>4-Operand Fused-Multiply-Add</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{aes|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{aes|}}}}} | <tr><th style="width: 100px;">AES</th><td>AES Encryption Instructions</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{rdrand|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{rdrand|}}}}} | <tr><th style="width: 100px;">RdRand</th><td>Hardware RNG</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{sha|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{sha|}}}}} | <tr><th style="width: 100px;">SHA</th><td>SHA Extensions</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{xop|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{xop|}}}}} | <tr><th style="width: 100px;">XOP</th><td>eXtended Operations Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{adx|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{adx|}}}}} | <tr><th style="width: 100px;">ADX</th><td>Multi-Precision Add-Carry</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{clmul|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{clmul|}}}}} | <tr><th style="width: 100px;">CLMUL</th><td>Carry-less Multiplication Extension</td></tr> }}<!-- |
| − | -->{{#if: {{istrue|{{{f16c|}}}}} | <tr><th style="width: | + | -->{{#if: {{istrue|{{{f16c|}}}}} | <tr><th style="width: 100px;">F16C</th><td>16-bit Floating Point Conversion</td></tr> }}<!-- |
--></table> | --></table> | ||
<table class="tl1"><!-- | <table class="tl1"><!-- | ||
Revision as of 15:41, 26 November 2016
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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