Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:x86 features"
(linked to AMD's SME/TSME/SEV) |
|||
| Line 74: | Line 74: | ||
-->{{#if: {{istrue|{{{amdvi|}}}}} | <tr><th style="width: 100px;">AMD-Vi</th><td>AMD-Vi (I/O MMU virtualization)</td></tr>[[has amd amd-vi technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdvi|}}}}} | <tr><th style="width: 100px;">AMD-Vi</th><td>AMD-Vi (I/O MMU virtualization)</td></tr>[[has amd amd-vi technology::true| ]] }}<!-- | ||
-->{{#if: {{istrue|{{{amdv|}}}}} | <tr><th style="width: 100px;">AMD-V</th><td>AMD Virtualization</td></tr>[[has amd amd-v technology::true| ]] }}<!-- | -->{{#if: {{istrue|{{{amdv|}}}}} | <tr><th style="width: 100px;">AMD-V</th><td>AMD Virtualization</td></tr>[[has amd amd-v technology::true| ]] }}<!-- | ||
| − | -->{{#if: {{istrue|{{{ | + | -->{{#if: {{istrue|{{{amdsme|}}}}} | <tr><th style="width: 100px;">SME</th><td>[[x86/sme|Secure Memory Encryption]]</td></tr>[[has amd secure memory encryption technology::true| ]] }}<!-- |
| − | -->{{#if: {{istrue|{{{ | + | -->{{#if: {{istrue|{{{amdtsme|}}}}} | <tr><th style="width: 100px;">TSME</th><td>[[x86/sme#Transparent_SME|Transparent SME]]</td></tr>[[has amd transparent secure memory encryption technology::true| ]] }}<!-- |
| − | -->{{#if: {{istrue|{{{ | + | -->{{#if: {{istrue|{{{amdsev|}}}}} | <tr><th style="width: 100px;">SEV</th><td>[[x86/sme#Secure_Encrypted_Virtualization|Secure Encrypted Virtualization]]</td></tr>[[has amd secure encrypted virtualization technology::true| ]] }}<!-- |
-->{{#if: {{istrue|{{{ept|}}}}} | <tr><th style="width: 100px;">EPT</th><td>[[has extended page tables support::true| ]]Extended Page Tables ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | -->{{#if: {{istrue|{{{ept|}}}}} | <tr><th style="width: 100px;">EPT</th><td>[[has extended page tables support::true| ]]Extended Page Tables ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | ||
-->{{#if: {{istrue|{{{rvi|}}}}} | <tr><th style="width: 100px;">RVI</th><td>Rapid Virtualization Indexing ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | -->{{#if: {{istrue|{{{rvi|}}}}} | <tr><th style="width: 100px;">RVI</th><td>Rapid Virtualization Indexing ([[has second level address translation support::true| ]][[Second Level Address Translation|SLAT]])</td></tr> }}<!-- | ||
Revision as of 04:05, 17 December 2017
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|
|
|
||
