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From WikiChip
Difference between revisions of "Template:interconnect arch"
| Line 9: | Line 9: | ||
| | | | ||
* [[accelerated graphics port|AGP]] | * [[accelerated graphics port|AGP]] | ||
| + | * [[CAPI]] | ||
* [[CCIX]] | * [[CCIX]] | ||
* [[extended industry standard architecture|EISA]] | * [[extended industry standard architecture|EISA]] | ||
| Line 18: | Line 19: | ||
* [[Multibus]] | * [[Multibus]] | ||
* {{nvidia|NVLink}} | * {{nvidia|NVLink}} | ||
| − | |||
* [[peripheral component interconnect|PCI]] | * [[peripheral component interconnect|PCI]] | ||
* [[peripheral component interconnect express|PCIe]] | * [[peripheral component interconnect express|PCIe]] | ||
