• intel
  ...er [[integrated circuit]]s including [[flash memory]], [[network interface controller]]s, [[GPU]]s, [[chipset]]s, motherboards, and computers. * {{\\|Programmable Unified Memory Architecture}} (PUMA)
  9 KB (1,150 words) - 00:03, 2 October 2022
• national semiconductor/cops ii
  The '''COP400''' or '''COPS II''' or simply '''COPS''' ('''Controller Oriented Processor System II''') was a [[microprocessor family|family]] of ...rocontrollers, one of the earliest instances of multiple CPUs in on single integrated circuit.
  6 KB (685 words) - 22:49, 5 February 2016
• intel/core i7/i7-4950hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  4 KB (404 words) - 16:22, 13 December 2017
• intel/core i7/i7-4960hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (401 words) - 14:24, 12 February 2019
• intel/core i7/i7-4980hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] called {{intel|Crystal Well}}.
  3 KB (400 words) - 16:22, 13 December 2017
• intel/core i7/i7-4860hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (399 words) - 16:22, 13 December 2017
• intel/core i7/i7-4870hq
  |max memory=32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (386 words) - 09:14, 26 December 2017
• intel/core i7/i7-4750hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-4760hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features a large 128 MB [[L4$]] cache called {{intel|Crystal We
  3 KB (397 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770hq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (398 words) - 16:22, 13 December 2017
• intel/core i7/i7-4770r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  4 KB (406 words) - 16:22, 13 December 2017
• intel/core i5/i5-4670r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  4 KB (404 words) - 16:19, 13 December 2017
• intel/core i5/i5-4570r
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (401 words) - 16:19, 13 December 2017
• intel/core i7/i7-4860eq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (396 words) - 16:22, 13 December 2017
• intel/core i7/i7-4850eq
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (391 words) - 16:22, 13 December 2017
• intel/xeon e3/e3-1284l v3
  | max memory = 32 GiB ...ell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  3 KB (399 words) - 16:27, 13 December 2017
• intel/celeron/3855u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (596 words) - 16:15, 13 December 2017
• intel/celeron/3955u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (596 words) - 16:15, 13 December 2017
• intel/core i3/i3-6098p
  |max memory=64 GiB ...of 1.05 GHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 ECC memory.
  4 KB (627 words) - 16:17, 13 December 2017
• intel/core i5/i5-6402p
  |max memory=64 GiB ...ency of 950 MHz. This chip supports up to 64 GiB of dual-channel DDR4-2133 memory.
  4 KB (627 words) - 16:20, 13 December 2017
• intel/core i7/i7-6498du
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (640 words) - 02:21, 16 January 2019
• intel/core i5/i5-6198du
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
  4 KB (650 words) - 02:21, 16 January 2019
• intel/core i7/i7-5500du
  | max memory = 32 GiB | max memory addr =
  5 KB (469 words) - 16:22, 13 December 2017
• intel/core i7/i7-5950hq
  | max memory = 32 GiB {{integrated graphic
  4 KB (407 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850hq
  | max memory = 32 GiB {{integrated graphic
  4 KB (401 words) - 16:22, 13 December 2017
• intel/core i7/i7-5850eq
  | max memory = 32 GiB {{integrated graphic
  4 KB (395 words) - 16:22, 13 December 2017
• intel/core i7/i7-5750hq
  | max memory = 32 GiB {{integrated graphic
  4 KB (424 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775r
  | max memory = 32 GiB {{integrated graphic
  4 KB (405 words) - 16:22, 13 December 2017
• intel/core i7/i7-5775c
  |max memory=32 GiB {{integrated graphic
  4 KB (460 words) - 15:03, 24 March 2019
• intel/core i5/i5-5675r
  | max memory = 32 GiB {{integrated graphic
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5675c
  | max memory = 32 GiB {{integrated graphic
  4 KB (454 words) - 18:17, 2 November 2019
• intel/core i5/i5-5575r
  | max memory = 32 GiB {{integrated graphic
  4 KB (409 words) - 16:19, 13 December 2017
• intel/core i5/i5-5350h
  | max memory = 32 GiB {{integrated graphic
  4 KB (415 words) - 16:19, 13 December 2017
• intel/core i3/i3-6167u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6167U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
  4 KB (631 words) - 16:18, 13 December 2017
• intel/core i5/i5-6287u
  |max memory=32 GiB ...Hz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6287U comes with an additional 64 MiB of [[embedded DRAM]] side cache.
  4 KB (649 words) - 16:20, 13 December 2017
• baikal/baikal-t1
  | max memory = 8 GiB == Memory controller ==
  3 KB (323 words) - 16:10, 13 December 2017
• motorola/mc14500
  ...replace older relay-based [[ladder logic]] as a cheap [[programmable logic controller]]. Production continued well into the 1990s. ...esigned by Motorola. Intended to serve as a very simple programmable logic controller and replace and simplify older machinery, the MC14500 cheap price and ease
  4 KB (538 words) - 10:44, 22 May 2018
• intel/atom
  ...Poulsbo|l=chipset}} chipset which features the [[memory controller]], an [[integrated graphics]], and the various [[I/O]] ports. ...on-die, including the [[memory controller]], [[display controller]], and [[integrated graphics]]. Lincroft, along with the {{intel|Moorestown|l=platform}}, model
  17 KB (2,292 words) - 09:32, 16 July 2019
• intel/atom x7/z8750
  | max memory = 8 GiB ...end mobile system on chips. This chip supports up to 8 GiB of memory and [[integrated graphics processor|integrates]] the {{intel|HD Graphics 405}} GPU.
  4 KB (462 words) - 16:15, 13 December 2017
• intel/atom x7/z8700
  | max memory = 8 GiB ...end mobile system on chips. This chip supports up to 8 GiB of memory and [[integrated graphics processor|integrates]] the {{intel|HD Graphics (Cherry Trail)}} GP
  4 KB (472 words) - 16:15, 13 December 2017
• intel/atom x5/x5-e8000
  |max memory=8 GiB ...equency of 1.04 GHz with a burst up to 2.0 GHz and supports up to 8 GiB of memory. This chip incorporates the {{intel|HD Graphics (Braswell)}} GPU.
  4 KB (475 words) - 17:42, 27 March 2018
• intel/atom x5/x5-z8500
  | max memory = 8 GiB | max memory addr =
  5 KB (573 words) - 16:15, 13 December 2017
• intel/atom x5/x5-z8550
  | max memory = 8 GiB | max memory addr =
  5 KB (572 words) - 16:15, 13 December 2017
• intel/atom x5/x5-z8300
  | max memory = 2 GiB | max memory addr =
  6 KB (744 words) - 18:35, 14 January 2019
• intel/atom x5/x5-z8350
  |max memory=2 GiB ...equency of 1.44 GHz with a burst up to 1.92 GHz and supports up to 2 GB of memory. This chip incorporates the {{intel|HD Graphics (Cherry Trail)}} GPU.
  5 KB (736 words) - 03:44, 19 August 2023
• intel/atom x5/x5-z8330
  | max memory = 2 GiB | max memory addr =
  5 KB (558 words) - 16:15, 13 December 2017
• intel/atom x3/x3-c3130
  | max memory = 1024 MB {{integrated graphic
  4 KB (424 words) - 16:15, 13 December 2017
• intel/atom x3/x3-c3230rk
  | max memory = 2 GiB {{integrated graphic
  4 KB (449 words) - 16:15, 13 December 2017
• intel/atom x3/x3-c3445
  | max memory = 2 GiB {{integrated graphic
  4 KB (467 words) - 16:15, 13 December 2017

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