• mirc/msl injection
  The timer will register that its associated command to be executed when the delay has passed is "ec '''By default BOTH $read() and $readini() treat the text in the file as code!'''
  26 KB (4,222 words) - 08:43, 21 January 2023
• mirc/commands/comreg
  ...s to make themselves accessible to applications. Regsvr32 command will not register .NET assemblies because of their very nature. However if you must, [http:// <syntaxhighlight lang="mIRC">;register example.dll file
  964 bytes (128 words) - 19:13, 15 June 2017
• multiplexer
  |symbol body = [[File:Mux 2 1.svg|150px|center]] |functional body = [[File:mux functional.gif|center]]
  10 KB (1,445 words) - 11:53, 18 November 2018
• hitachi/hmcs-4
  ...e of 4 chips. The chipset included a [[ROM]] chip, a [[RAM]] chip, [[shift register]], and a [[4-bit architecture|4-bit]] [[microprocessor]]. The chipset was f | {{hitachi|HD35403}} || Shift Register
  2 KB (266 words) - 00:54, 19 May 2016
• intel/mcs-40/4040
  ...l set of additional instructions, a larger call stack, a larger [[register file]], and interrupt capabilities. The package size was also increased to 24 pi ...roduced interrupt support. 14 new instructions were added and the register file was increased to 24 index registers.
  1 KB (178 words) - 16:24, 13 December 2017
• 4-bit architecture
  ...or a [[nibble]]. These architectures typically have a matching [[register file]] with [[registers]] width of 4 bits and 4-8-bit wide addresses. * [[HP Saturn]] (64-bit register, 4-bit data path)
  4 KB (580 words) - 10:37, 12 December 2020
• digital design
  [[File:Digital Design.svg|300px|right]] ...aditionally, digital design dealt with [[Logic gate|gate]]-level design ([[register-transfer level]]), synthesis of HDLs (such as [[VHDL]] and [[Verilog]]), an
  682 bytes (91 words) - 12:10, 21 July 2018
• immediate value
  ...of the instruction itself instead of being in a [[memory]] location or a [[register]]. Immediate values are typically used in instructions that [[Load/Store in ...consider an ISA that can add two registers and store the result in a third register:
  2 KB (387 words) - 10:09, 28 August 2020
• 1-bit architecture
  ...] width of 1 bit. These architectures typically have a matching [[register file]] with [[registers]] width of 1 bit. Very few 1-bit architecture CPUs were
  1 KB (191 words) - 15:45, 21 March 2024
• 8-bit architecture
  ...or an [[octet]]. These architectures typically have a matching [[register file]] with [[registers]] width of 8 bits.
  2 KB (232 words) - 10:18, 24 June 2017
• 2-bit architecture
  ...width of 2 bits. These architectures typically have a matching [[register file]] with [[registers]] width of 2 bits. Very few 2-bit architecture CPUs were
  511 bytes (62 words) - 23:59, 16 January 2016
• 12-bit architecture
  ...r 1.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 12 bits.
  679 bytes (83 words) - 14:36, 7 October 2016
• 16-bit architecture
  ...or 2 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 16 bits.
  1 KB (135 words) - 13:16, 20 July 2018
• 20-bit architecture
  ...r 2.5 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 20 bits.
  410 bytes (50 words) - 00:02, 17 January 2016
• amd/am2900
  | {{\|AM2918}}<br />{{\|AM29LS18}} || Quad D register with standard and 3-state outputs || 16, 20 | {{\|AM2919}} || Quad D register with dual 3-state outputs || 20
  9 KB (1,061 words) - 22:55, 18 June 2019
• national semiconductor/cops i
  | {{\|MM57126}} || [[shift register]] * [[:File:National COPS Databook (1977).pdf|National COPS Databook, 1977]]
  2 KB (274 words) - 18:29, 5 February 2016
• discrete logic
  ...ght|thumb|250px|An implementation of a [[4-bit architecture|4-bit]], two [[register]] computer made using individual [[7400 series]] [[IC]]s.]]
  1 KB (163 words) - 06:06, 18 December 2015
• 7400 series
  [[File:7400_Series_Chips_1.jpg|thumb|right|250px|A series of various 74LS chips.]] ...te logic chip]]s chips such as [[and gates]] and [[or gates]] as well as [[register]]s, [[decoder]]s, and [[RAM]] units.
  7 KB (851 words) - 20:53, 29 July 2021
• intel/mcs-4
  [[File:1971 Intel Advertisement.jpg|250px|thumbnail|right|An ad for the MCS-4 in t ...U]], however its designed to be fully functioning with [[RAM]] and [[shift register]]. Additionally two more chips, the [[/4008|4008]] and [[/4009|4009]], expa
  4 KB (433 words) - 22:40, 27 June 2019
• 24-bit architecture
  ...or 3 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 24 bits.
  484 bytes (58 words) - 11:06, 28 May 2017
• 32-bit architecture
  ...or 4 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 32 bits.
  1 KB (137 words) - 19:55, 5 December 2019
• 64-bit architecture
  ...or 8 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 64 bits.
  2 KB (240 words) - 02:48, 17 March 2019
• 15-bit architecture
  ...width of 15 bits. These architectures typically have a matching [[register file]] with [[registers]] width of 15 bits.
  372 bytes (47 words) - 00:26, 17 January 2016
• 18-bit architecture
  ...width of 18 bits. These architectures typically have a matching [[register file]] with [[registers]] width of 18 bits.
  419 bytes (53 words) - 00:50, 17 January 2016
• nec/μcom-42/μpd548
  ...ily}}. This microcontroler was designed specifically for [[electronic cash register]]s, [[point of sale]]s, and electronic scales. * [[:File:NEC μPD548.pdf|NEC μPD548 datasheet]]
  2 KB (183 words) - 05:49, 20 January 2016
• motorola/mc14500/mc14500b
  The MC14500B had a single 1-bit register to hold the result and supported {{motorola|mc14500/isa|16 different operat * [[:File:MC14500B datasheet.pdf|MC14500B Datasheet]]
  2 KB (232 words) - 16:31, 13 December 2017
• motorola/mc14500
  The MC14500B has a single register (the result register) and supports 16 different operations. * [[:File:Motorola MC14500B Industial Control Unit Handbook.pdf|Motorola MC14500B Ind
  4 KB (538 words) - 10:44, 22 May 2018
• 36-bit architecture
  ...idth of 36 bits . These architectures typically have a matching [[register file]] with [[registers]] width of 36 bits. 36-bit systems allowed for the manip
  578 bytes (67 words) - 07:19, 27 June 2018
• intel/microarchitectures/bonnell
  [[File:intel low-power roadmap (45-32-22).png|500px|right|thumb|[[45 nm]] - [[32 n | [[File:intel centrino atom logo.png|100px]] ||
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  :[[File:bonnell pipeline.svg]] *** reading [[register]] operand
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  [[File:silvermont block.png]] [[File:silvermont modules.svg|right|450px]]
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  [[File:haswell buff window.png|right|350px]] ** Integer register file up 8 entries to 168
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  [[File:intel gesher.jpg|left|150px]] | rowspan="2" | [[File:intel celeron (2009).png|60px|link=intel/celeron]] || rowspan="2" | {{inte
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  | rowspan="2" | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || rowspan="2" | {{inte | rowspan="2" | [[File:intel pentium (2015).png|50px|link=intel/pentium_(2009)]] || rowspan="2" |
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/am386
  ...quiring a separate static RAM chip to store machine state (e.g. [[register file]]) when in maximum saving during sleep mode. In addition to sleep mode, the [[File:ADVANCED MICRO DEVICES Am386 TM DX-40 NG80386DX-40 D 313NFY9 m AMD 5983D 93
  8 KB (1,077 words) - 14:50, 2 April 2020
• intel/80486
  ...f received some attention as well. Simple ALU ''register, register'' and ''register, [[immediate value|immediate]]'' cached operations could now complete in a * [[:File:486 DX2 Microprocessor Data Book (February 1992).pdf|486 DX2 Microprocessor
  8 KB (953 words) - 08:27, 29 October 2022
• 128-bit architecture
  ...or 16 [[octet]]s. These architectures typically have a matching [[register file]] with [[registers]] width of 64 bits.
  593 bytes (81 words) - 09:51, 20 July 2018
• cmu/piperench
  ...idual ''stripes''. Each strip has a set of simple execution units (EU/PE), register files, and a interconnection network. By configuring each of the stripes us [[File:cmu piperench die.jpg|450px]]
  3 KB (337 words) - 16:13, 13 December 2017
• ambric/am2000
  | [[File:Am2045 die shot.png]] || [[File:Am2045 die shot (annotated).png]] [[File:ambric neighbor channels.png|thumb|right|350px|'''Neighbor Channels''']]
  11 KB (1,421 words) - 14:45, 9 December 2018
• mathstar/builder
  [[File:mathstar layout.png|right]] ...c Redundancy Check]] (CRC), [[Multiply Accumulator]] (MAC), and [[Register File]] (RF). The control program guides the overall program execution and the da
  5 KB (596 words) - 21:23, 19 November 2017
• mathstar/arrix
  * 80x [[register file|RFs]] [[File:arrix chip layout.png|600px]]
  4 KB (492 words) - 00:37, 28 June 2016
• intrinsity/fastmath
  ...-point matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache. [[File:eval board.jpg|right|thumb|Evaluation Board]]
  4 KB (464 words) - 17:41, 3 July 2016
• microarchitecture
  ...[[transistors]] and [[resistors]] to more complex units such as [[register file]]s and [[multipliers]] to complete elements such as [[arithmetic logic unit ...or [[VHDL]]. The description of the circuit is known as [[RTL design]]. [[Register Transfer Level]] (RTL) can be efficiently described using HDL. Final RTL de
  3 KB (431 words) - 22:51, 21 November 2017
• amd/microarchitectures/zen
  [[File:amd-zen-black-logo.png|right|Zen Logo]] [[File:amd ryzen black bg logo.png|thumb|right|Ryzen brand logo]]
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  [[File:amd zen 2 logo.png|right|thumb|Zen 2]] [[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]]
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  [[File:iris graphics logo.svg|right|200px]] [[File:kaby lake soc block diagram.svg|900px]]
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  [[File:iris graphics logo.svg|right|200px]][[File:iris pro graphics logo.svg|right|200px]] [[File:skylake soc block diagram.svg|900px]]
  33 KB (4,255 words) - 17:41, 1 November 2018
• phytium/microarchitectures/xiaomi
  [[File:xiaomi block diagram.svg]] [[File:phytium xiaomi predictor.png|thumb|right|predictor]]
  7 KB (940 words) - 00:12, 8 March 2021
• acorn/microarchitectures/arm1
  [[File:arm1 block diagram.svg|700px]] : [[File:arm1 pipeline.svg|800px]]
  12 KB (1,886 words) - 12:56, 14 January 2021
• amd/microarchitectures/zen 3
  [[File:amd zen future roadmap.jpg|400px|right]] [[File:amd zen2-3 roadmap.png|thumb|right|Zen 3 on the roadmap]]
  15 KB (1,978 words) - 22:13, 6 April 2023

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