• mediatek/helio/mt6755t
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  4 KB (552 words) - 23:18, 3 November 2019
• mediatek/helio/mt6757cd
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  4 KB (564 words) - 06:22, 30 March 2021
• intel/microarchitectures/gen9.5
  ** Can be coupled with decoder to allow high-quality video processing in the FF units in the unslice witho
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ** Can be coupled with decoder to allow high-quality video processing in the FF units in the unslice witho
  33 KB (4,255 words) - 17:41, 1 November 2018
• intel/microarchitectures/merced
  ** No decoder necessary
  7 KB (978 words) - 21:16, 20 January 2021
• renesas/r-car/v2h
  * Five-channel low-delay H.264/JPEG decoder
  2 KB (346 words) - 16:32, 13 December 2017
• samsung/microarchitectures/m1
  ...instruction queue]] the instructions are sent to decode. Decode is a 4-way decoder which can handle both the [[ARM]] {{arm|AArch64}} and {{arm|AArch32}} instr
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  ...les]] and deliver a large number of instructions to be decoded by a larger decoder. With up to 12 instructions fetched each time, the M3 is effectively fetchi [[File:m3 decode.svg|thumb|right|M3 features a 6-way decoder.]]
  20 KB (3,149 words) - 10:44, 15 February 2020
• cavium/microarchitectures/vulcan
  ** New Decoder ...uent instructions where they are queued to go for the [[instruction decode|decoder]]. The queue is shared by all threads. The size of the queue has not been d
  17 KB (2,449 words) - 22:11, 4 October 2019
• nvidia/microarchitectures/denver
  ...ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are Denver is 7-wide in-order superscalar. It has ARMv8 hardware decoder (A32, T32, and A64 modes) which can generate up to 2 micro-ops per cycle. A
  6 KB (825 words) - 09:10, 11 February 2020
• intel/microarchitectures/sunny cove
  ...e’s 4 way wide decoder to 4 simple + 1 complex in Sunny cove 5 way wide decoder) ...properties such as branches. As with previous microarchitectures, the pre-decoder has a [[throughput]] of 6 [[macro-ops]] per cycle or until all 16 bytes are
  34 KB (5,187 words) - 06:27, 17 February 2023
• bitmain/sophon/bm1880
  * H.264 Video decoder * MJPEG encoder/decoder
  2 KB (263 words) - 12:19, 25 December 2018
• intel/microarchitectures/gracemont
  *** Add OD-ILD (on-demand instruction length decoder)
  2 KB (194 words) - 05:24, 1 September 2023
• intel/microarchitectures/golden cove
  ** Add 2 simple decoders from 5 but canceled the complex decoder design as it is no longer practical and complex instructions can now be han
  2 KB (261 words) - 10:14, 1 September 2022
• arm holdings/microarchitectures/mlp
  ...ly operations. The weights for each set of operations come from the weight decoder while the assembled tensor of activations comes from broadcast network. Arm
  9 KB (1,379 words) - 22:35, 6 February 2020
• arm holdings/microarchitectures/cortex-a510
  *** Wider decoder (3-way, up from 2-way)
  15 KB (2,282 words) - 11:20, 10 January 2023

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