• cea-leti/microarchitectures/tsarlet
  * L1 Cache ** L1 Instruction cache
  12 KB (1,895 words) - 10:17, 27 March 2020
• amd/cores/seattle
  ** 4 core complexes, each comprising 2 CPU cores and 1 MiB shared L2 cache ** 8 × 48 KiB L1 instruction cache, 3-way set associative, parity protected
  3 KB (380 words) - 14:32, 17 March 2023
• arm holdings/microarchitectures/neoverse v1
  ** New L0 MOP cache The Neoverse N1 has a private L1I, L1D, and L2 cache.
  5 KB (748 words) - 16:20, 4 July 2022
• alchemy/microarchitectures/au1
  ...the data cache continues to snoop the internal System Bus to maintain data coherency. The {{abbr|GPR}}s and CP0 registers are preserved in both modes, the CP0 C ...by software. It does not recognize Soft Reset, Non-Maskable Interrupt, or Cache Error exception conditions.
  13 KB (2,114 words) - 16:00, 17 April 2022
• alchemy/alchemy
  ...se modes the data cache remains operational, snooping the SBUS to maintain coherency. {{abbr|GPR}}s and CP0 registers are preserved in both modes, the CP0 const
  31 KB (4,972 words) - 03:09, 20 March 2022
• annapurna labs/graviton/graviton4
  ...er. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be co == Cache ==
  4 KB (586 words) - 01:50, 12 December 2023

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