Semiconductor & Computer Engineering
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- hdel -w <table_name> <wild_item> If the -w switch is used, a {{mirc|wildcard}} pattern for the item can be specified t30 KB (5,149 words) - 01:46, 30 November 2018
- |0001 1001||031 || 25||19||EM||End of Medium |0010 0101||045 || 37||25||LF||Line Feed9 KB (885 words) - 07:19, 10 December 2013
- | {{\|X1000}} || October 8, 2013 || 1 || 1 || 400 MHz || 32 nm || 2.2 W || 16kB || [[FCBGA393]] | {{\|X1001}} || April 11, 2014 || 1 || 1 || 400 MHz || 32 nm || 2.2 W || 16kB || [[FCBGA393]]4 KB (434 words) - 03:31, 15 February 2016
- * '''TDP:''' 45 W * '''TDP:''' 18, 25, 35 W43 KB (5,739 words) - 21:30, 22 April 2024
- ;draw a red line size = 3, first point = 25 50, second point 75 50 .timer 1 2 drawline -r @test 255 3 25 50 75 5011 KB (1,875 words) - 14:15, 20 October 2018
- |core family=25 |tdp=320 W4 KB (693 words) - 01:48, 2 April 2023
- |clock multiplier=25 |core family=254 KB (666 words) - 01:48, 2 April 2023
- ...{7seg|K|10}}), ''M'' ({{7seg|M|10}}), ''V'' ({{7seg|V|10}}), ''W'' ({{7seg|W|10}}), ''X'' ({{7seg|X|10}}), and ''Z'' ({{7seg|Z|10}}) are completely unre ...|| 1 || 1 || 0 || 1 || 1 || 1 || 0x77 || 0x77 || {{7seg|A|10}} || rowspan="25" | [[File:7 segment display labeled.svg|200px]]7 KB (905 words) - 00:16, 23 May 2022
- :'''25''' - 4-input [[NOR]] :'''W''' - [[ceramic flat pack|CFP]]7 KB (851 words) - 20:53, 29 July 2021
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (404 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (401 words) - 14:24, 12 February 2019
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (399 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (400 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (399 words) - 16:22, 13 December 2017
- |clock multiplier=25 |tdp=47 W3 KB (386 words) - 09:14, 26 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (401 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (397 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (398 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (406 words) - 16:22, 13 December 2017
- | tdp = 65 W | max bandwidth = 25,600 MB/s4 KB (404 words) - 16:19, 13 December 2017
- | tdp = 65 W | max bandwidth = 25,600 MB/s3 KB (401 words) - 16:19, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (396 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (391 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s3 KB (399 words) - 16:27, 13 December 2017
- |tdp=15 W |ctdp down=10 W4 KB (596 words) - 16:15, 13 December 2017
- |tdp=15 W |ctdp down=10 W4 KB (596 words) - 16:15, 13 December 2017
- |tdp=54 W |tstorage min=-25 °C4 KB (627 words) - 16:17, 13 December 2017
- |tdp=65 W |tstorage min=-25 °C4 KB (627 words) - 16:20, 13 December 2017
- |clock multiplier=25 |tdp=15 W4 KB (640 words) - 02:21, 16 January 2019
- |tdp=15 W |ctdp down=7.5 W4 KB (650 words) - 02:21, 16 January 2019
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (407 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (401 words) - 16:22, 13 December 2017
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (395 words) - 16:22, 13 December 2017
- | clock multiplier = 25 | tdp = 47 W4 KB (424 words) - 16:22, 13 December 2017
- |tdp=65 W |ctdp down=37 W4 KB (460 words) - 15:03, 24 March 2019
- | tdp = 65 W | ctdp down = 37 W4 KB (454 words) - 18:17, 2 November 2019
- | tdp = 47 W | max bandwidth = 25,600 MB/s4 KB (415 words) - 16:19, 13 December 2017
- |tdp=28 W |ctdp down=23 W4 KB (631 words) - 16:18, 13 December 2017
- |tdp=28 W |ctdp down=23 W4 KB (649 words) - 16:20, 13 December 2017
- | tdp = 5 W | package 0 width = 25 mm3 KB (323 words) - 16:10, 13 December 2017
- registers is called the W register. and the W register, can be used as a 32 bit accumulator called the31 KB (2,938 words) - 14:54, 17 March 2016
- ...ed introducing more aggressive gate length scaling. For example, their [[0.25 µm process]] had <code>L<sub>g</sub> = 0.20 µm</code> and likewise, their At the [[45 nm process]], Intel reached a gate length of 25 nm on a traditional [[planar transistor]]. At that node the gate length sca8 KB (1,225 words) - 13:48, 14 December 2022
- ...0|Athlon X4 530}} || Jaguar || 2.0 GHz || 4 || 4 || 28 nm || 1x2 MB || 25 W || 2014-09 ...0|Athlon X4 550}} || Jaguar || 2.2 GHz || 4 || 4 || 28 nm || 1x2 MB || 25 W || 2014-093 KB (333 words) - 21:33, 27 May 2023
- ...}} || Piledriver || 3.4 GHz || 4.0 GHz || 4 || 4 || 32 nm || 2x2 MB || 65 W || July 2012 ...|| Piledriver || 3.08 GHz || 4.2 GHz || 4 || 4 || 32 nm || 2x2 MB || 100 W || October 1, 20126 KB (619 words) - 05:05, 2 January 2019
- | sdp = 2 W | max bandwidth = 25,600 MB/s4 KB (462 words) - 16:15, 13 December 2017
- | sdp = 2 W | max bandwidth = 25,600 MB/s4 KB (472 words) - 16:15, 13 December 2017
- |tdp=5 W ...early 2016. This ultra-low power SoC has a thermal design power of just 5 W and operates at a base frequency of 1.04 GHz with a burst up to 2.0 GHz and4 KB (475 words) - 17:42, 27 March 2018
- | sdp = 2 W ...] in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz an5 KB (573 words) - 16:15, 13 December 2017
- | sdp = 2 W ...] in early 2016. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz and supports up to 8 GiB of me5 KB (572 words) - 16:15, 13 December 2017
- | sdp = 2 W | temp min = -25 °C4 KB (449 words) - 16:15, 13 December 2017
- | sdp = 2 W | temp min = -25 °C4 KB (467 words) - 16:15, 13 December 2017
- | sdp = 2 W | temp min = -25 °C4 KB (418 words) - 16:15, 13 December 2017
- | sdp = 2 W | temp min = -25 °C4 KB (412 words) - 16:15, 13 December 2017
- |tdp=6.5 W | bandwidth dchan = 25,600 MB/s4 KB (529 words) - 17:41, 27 March 2018
- |sdp=4 W |tdp=6 W5 KB (701 words) - 17:40, 27 March 2018
- |sdp=4 W |tdp=6 W4 KB (540 words) - 17:40, 27 March 2018
- |sdp=3 W |tdp=4 W4 KB (544 words) - 17:43, 27 March 2018
- |sdp=4 W |tdp=6 W4 KB (580 words) - 09:40, 8 July 2022
- |sdp=4 W |tdp=6 W5 KB (724 words) - 06:10, 2 December 2018
- |sdp=3 W |tdp=4 W4 KB (539 words) - 17:39, 27 March 2018
- |sdp=3 W |tdp=4 W4 KB (535 words) - 17:39, 27 March 2018
- |sdp=4 W |tdp=6 W5 KB (722 words) - 01:50, 24 November 2018
- |tdp=6 W | bandwidth dchan = 25,600 MB/s4 KB (533 words) - 17:41, 27 March 2018
- |tdp=6 W | bandwidth dchan = 25,600 MB/s4 KB (539 words) - 17:39, 27 March 2018
- |extension 25=ADCX ** Larger instruction queue (25 entries/thread, up from 20)14 KB (1,891 words) - 14:37, 6 January 2022
- |extension 25=ADCX ...hasis on mobile with models ranging from as low as 4.5 W to as high as 100 W.79 KB (11,922 words) - 06:46, 11 November 2022
- |extension 25=ADCX ...d. Previously, the dual-port Titan Ridge controller had a TDP of up to 2.4 W, so the overall saving is fairly sizable. The additional power saving thus23 KB (3,613 words) - 12:31, 20 June 2021
- | clock multiplier = 25 | tdp = 130 W4 KB (415 words) - 16:24, 13 December 2017
- | tdp = 130 W ...hip supports up to 24 GiB of memory and has a thermal design power of 130 W.4 KB (415 words) - 16:24, 13 December 2017
- | clock multiplier = 25 | tdp = 130 W4 KB (419 words) - 16:24, 13 December 2017
- | tdp = 130 W ...MPU supports up to 24 GiB of memory and has a thermal design power of 130 W.4 KB (414 words) - 16:24, 13 December 2017
- |tdp=140 W |l3 cache=25 MiB4 KB (564 words) - 14:29, 24 March 2019
- |clock multiplier=25 |idle power=4 W5 KB (710 words) - 16:24, 13 December 2017
- |idle power=4 W |tdp=55 W5 KB (710 words) - 03:49, 26 June 2018
- | tdp = 55 W | ctdp down = 45 W5 KB (573 words) - 16:24, 13 December 2017
- |tdp=55 W |ctdp down=45 W4 KB (558 words) - 23:13, 12 March 2019
- | tdp = 57 W ...}} microarchitecture and manufactured in [[22 nm process]] has a TDP of 57 W and supports up to 32 GiB of memory (DDR3).5 KB (544 words) - 16:24, 13 December 2017
- | tdp = 57 W ...}} microarchitecture and manufactured in [[22 nm process]] has a TDP of 57 W and supports up to 32 GiB of memory (DDR3).5 KB (542 words) - 16:24, 13 December 2017
- |tdp=15 W |ctdp down=9.5 W4 KB (649 words) - 16:22, 13 December 2017
- |tdp=15 W |ctdp down=9.5 W4 KB (649 words) - 16:22, 13 December 2017
- |tdp=15 W |ctdp down=7.5 W4 KB (654 words) - 17:22, 26 March 2018
- | first launched = January 25, 1999 | tdp = 10.3 W3 KB (366 words) - 16:25, 13 December 2017
- | first launched = January 25, 1999 | tdp = 11.6 W3 KB (360 words) - 16:25, 13 December 2017
- | first launched = January 25, 1999 | tdp = 11.8 W3 KB (320 words) - 16:25, 13 December 2017
- | first launched = January 25, 1999 | tdp = 13.1 W3 KB (309 words) - 16:25, 13 December 2017
- |tdp=80 W |tstorage min=-25 °C3 KB (485 words) - 00:29, 7 April 2018
- |tdp=80 W |tstorage min=-25 °C4 KB (620 words) - 00:27, 7 April 2018
- |tdp=80 W |tstorage min=-25 °C3 KB (490 words) - 00:29, 7 April 2018
- |tdp=45 W |tstorage min=-25 °C3 KB (489 words) - 16:26, 13 December 2017
- |tdp=80 W |tstorage min=-25 °C4 KB (609 words) - 00:29, 7 April 2018
- |tdp=25 W |tstorage min=-25 °C3 KB (484 words) - 16:26, 13 December 2017
- |tdp=80 W |tstorage min=-25 °C3 KB (490 words) - 00:29, 7 April 2018
- |tdp=25 W |tstorage min=-25 °C4 KB (608 words) - 16:26, 13 December 2017
- |tdp=80 W |tstorage min=-25 °C3 KB (506 words) - 00:29, 7 April 2018
- |tdp=80 W |tstorage min=-25 °C4 KB (620 words) - 00:24, 7 April 2018
- |tdp=80 W |tstorage min=-25 °C3 KB (490 words) - 00:29, 7 April 2018
- |tdp=35 W |tstorage min=-25 °C4 KB (624 words) - 00:27, 7 April 2018
- |tdp=45 W |ctdp down=35 W4 KB (648 words) - 16:27, 13 December 2017
- |tdp=45 W |ctdp down=35 W4 KB (646 words) - 05:24, 14 July 2018
- |tdp=45 W |ctdp down=35 W4 KB (654 words) - 16:27, 13 December 2017
