This is a number property representing the maximum number of PCIe lanes that are directly going to the chip in context. This number DOES NOT include lanes that come from auxiliary chips such as the southbridge. Note that this number usually refers to the number of usable PCIe as opposed to an absolute max as on some platforms (e.g., Intel's DMI 1/2/3) a set number of lanes are reserved for the chipset.

• Note: this property is currently an (older) duplicate of Property:io pcie max lanes

Pages using the property "max pcie lanes"

Showing 20 pages using this property.

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C
Core M 5Y31 +	12  +
Core M 5Y51 +	12  +
Core M 5Y70 +	12  +
Core M 5Y71 +	12  +
Core m3-6Y30 - Intel +	10  +
Core M3-7Y30 - Intel +	10  +
Core M3-7Y32 - Intel +	10  +
Core M3-8100Y - Intel +	10  +
Core M3-8114Y - Intel +	10  +
Core m5-6Y54 - Intel +	10  +
Core m5-6Y57 - Intel +	10  +
Core m7-6Y75 - Intel +	10  +
E
EPYC 7251 - AMD +	128  +
EPYC 7261 - AMD +	128  +
EPYC 7281 - AMD +	128  +
EPYC 7301 - AMD +	128  +
EPYC 7351 - AMD +	128  +
EPYC 7351P - AMD +	128  +
EPYC 7371 - AMD +	128  +
EPYC 7401 - AMD +	128  +