The '''8 µm lithography process''' (8-micron) was the semiconductor process technology used for early FET devices by leading semiconductor companies during the late early 1970s. This process had a smallest feature or gate length of roughly 8 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this process at companies such as [[Fairchild]] and [[TI]] was 2-inch (51 mm). This process was later superseded by [[6 µm]], [[5 µm]], and [[3 µm]] processes.

The 8-micron process was used by Intel for many of their memory chips in the early 1970s such as the {{intel|2104}} which was released in 1972 and became the first truly widely used DRAM chip. Those chips used Si-gate [[nMOS]] transistors using a polysilicon word line and an aluminum metal bit line. Alternatively to that was Mostek's which created a 4 Kib chip using an aluminum metal word line and drain diffusion for the bit line<ref>Rideout, V. Leo. "One-device cells for dynamic random-access memories: A tutorial." IEEE Transactions on Electron Devices 26.6 (1979): 839-852.</ref>.

 

| compare

 

 

| fab 3 xtor.type  = Planar

  | fab 3 xtor.volt  = 5 V

  | fab 3 layers      =

  | fab 3 diff from  = [[10 µm]] Δ

  | fab 3 xtor.lg    = 8 µm

  | fab 3 xtor.lgΔ    = 0.80x

  | fab 3 xtor.cpp    =

 

| fab 4 name        = MOS Technology

  | fab 4 proc name  =

 

** {{intel|1103}}, 1 Kib DRAM, world's first commercial DRAM