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{{lithography processes}} | {{lithography processes}} | ||
− | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin | + | The '''3 nanometer (3 nm or 30 Å) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[5 nm lithography process|5 nm process]] node. Commercial [[integrated circuit]] manufacturing using 3 nm process is set to begin sometimes around 2023. |
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | ||
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<!-- Intel --> | <!-- Intel --> | ||
| process 1 fab = [[Intel]] | | process 1 fab = [[Intel]] | ||
− | | process 1 name = | + | | process 1 name = P1280? (CPU), P1281? (SoC) |
− | | process 1 date = | + | | process 1 date = |
| process 1 lith = EUV | | process 1 lith = EUV | ||
| process 1 immersion = | | process 1 immersion = | ||
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| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
− | | process 1 transistor = | + | | process 1 transistor = |
| process 1 volt = | | process 1 volt = | ||
| process 1 delta from = [[5 nm]] Δ | | process 1 delta from = [[5 nm]] Δ | ||
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<!-- TSMC --> | <!-- TSMC --> | ||
| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = | + | | process 2 name = |
− | | process 2 date = | + | | process 2 date = |
| process 2 lith = EUV | | process 2 lith = EUV | ||
| process 2 immersion = | | process 2 immersion = | ||
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| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
| process 2 wafer size = 300 mm | | process 2 wafer size = 300 mm | ||
− | | process 2 transistor = | + | | process 2 transistor = |
| process 2 volt = | | process 2 volt = | ||
| process 2 delta from = [[5 nm]] Δ | | process 2 delta from = [[5 nm]] Δ | ||
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<!-- Samsung --> | <!-- Samsung --> | ||
| process 4 fab = [[Samsung]] | | process 4 fab = [[Samsung]] | ||
− | | process 4 name = | + | | process 4 name = 3GAAE<info>3nm Gate All Around Early</info> |
| process 4 date = | | process 4 date = | ||
| process 4 lith = EUV | | process 4 lith = EUV | ||
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| process 4 dram Δ = | | process 4 dram Δ = | ||
}} | }} | ||
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=== Samsung === | === Samsung === | ||
On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown. | On May 24 2017 Samsung announced they will be switching to a transistor they call ''Multi-Bridge-Channel FET'' (''MBCFET''), an extension of a [[Gate-all-around]] (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown. | ||
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== 3 nm Microprocessors== | == 3 nm Microprocessors== | ||
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{{expand list}} | {{expand list}} | ||