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| | {{lithography processes}} | | {{lithography processes}} |
| − | The '''350 nanometer lithography process''' (350 nm or 0.35 µm) is a [[technology node|full node]] semiconductor manufacturing process following the [[500 nm lithography process|500 nm process]] node. Commercial [[integrated circuit]] manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by [[250 nm]] in 1999. | + | The '''350 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[500 nm lithography process|500 nm process]] node. Commercial [[integrated circuit]] manufacturing using 350 nm process began in late 1995. 350 micron and was phased our and replaced by [[250 nm]] in 1998. |
| − | | |
| − | == Industry ==
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| − | {{scrolling table/top|style=text-align: right; | first=Fab
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| − | |Process Name
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| − | |1st Production
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| − | |Voltage
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| − | |Metal Layers
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| − | |
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| − | |Gate Oxide
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| − | |Contacted Gate Pitch
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| − | |Interconnect Pitch (M1P)
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| − | |SRAM bit cell
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| − | }}
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| − | {{scrolling table/mid}}
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| − | |-
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| − | ! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[AMD]] || colspan="2" | [[DEC]] || colspan="2" | [[Fujitsu]] || colspan="2" | [[IDT]] || colspan="2" | [[NEC]] || colspan="2" | [[TI]] || colspan="2" | [[Motorola]] || colspan="2" | [[Hitachi]] || [[Планар]] <ref>http://kb-omo.by/content/view/1080/599/</ref>
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| − | |- style="text-align: center;"
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| − | | colspan="2" | P854 || colspan="2" | || colspan="2" | CS-34 || colspan="2" | CS-34EX || colspan="2" | CMOS-6 || colspan="2" | CS-60 || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | HiPerMOS 2 || colspan="2" | || colspan="2" | КМОП 0,35
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| − | |- style="text-align: center;"
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| − | | colspan="2" | 1994 || colspan="2" | 1994 || colspan="2" | 1995 || colspan="2" | || colspan="2" | 1995 || colspan="2" | 1996 || colspan="2" | 1996 || colspan="2" | 1995 || colspan="2" | 1997 || colspan="2" | 1996 || colspan="2" | || colspan="2" |1997
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| − | |- style="text-align: center;"
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| − | | colspan="2" | 3.3 V || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | || colspan="2" | 3,3V - 5V
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| − | |- style="text-align: center;"
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| − | | colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 5 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | 3 || colspan="2" | 4 || colspan="2" | 5 || colspan="2" | || colspan="2" |
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| − | |-
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| − | ! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[500 nm]] Δ !! Value !! [[600 nm]] Δ
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| − | |-
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| − | | || || || || || || || || 6.5 nm || || || || || || || || || || || || || ||
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| − | |-
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| − | | 550 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x
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| − | |-
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| − | | 880 nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || 750 nm || ?x
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| − | |-
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| − | | 18.1 µm² || 0.41x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || ? µm² || ?x || 21.67 µm² || ?x || ? µm² || ?x|| 18 µm² || ?x
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| − | {{scrolling table/end}}
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| − | === Intel ===
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| − | {| class="wikitable collapsible collapsed"
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| − | |-
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| − | ! colspan="3" | Intel 0.350 micron Design Rules
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| − | |-
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| − | ! Layer !! Pitch !! Thick
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| − | |-
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| − | | Isolation || ? nm || ? nm
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| − | |-
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| − | | Polysilicon || ? nm || ? nm
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| − | |-
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| − | | Metal 1 || 880 nm || 600 nm
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| − | |-
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| − | | Metal 2 || 1.16 µm || 800 nm
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| − | |-
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| − | | Metal 3 || 1.16 µm || 800 nm
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| − | |-
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| − | | Metal 4 || 1.70 µm || 1.70 µm
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| − | |}
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| − | === DEC ===
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| − | DEC's 0.35 µm process, called ''CMOS-6'', was designed at Fab-6 in Hudson, Mass. The process uses a Cobalt-Disilicide [[Salicide]] with L<sub>drawn</sub> of 0.35 µm with an L<sub>eff</sub> of 0.25 µm with a T<sub>ox</sub> of 6 nm. CMOS-6 was used for a number of DEC's processors such as Alpha and StrongARM. The plant was later sold to [[Intel]] where it continued to manufacture Intel's line of {{intel|XScale|l=arch}} processors.
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| − | | |
| − | == 350 nm Microprocessors==
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| − | * Intel
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| − | ** {{intel|pentium (1992)|Pentium}}
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| − | ** {{intel|Pentium MMX}}
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| − | ** {{intel|Pentium OverDrive MMX}}
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| − | ** {{intel|Pentium II}}
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| − | ** {{intel|Mobile Pentium II}}
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| − | * AMD
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| − | ** {{amd|Am5x86}}
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| − | ** {{amd|Am486#Enhanced Am486|Enhanced Am486}}
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| − | ** {{amd|K5}}
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| − | ** {{amd|K6}}
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| − | * DEC
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| − | ** {{decc|Alpha 21164A}}
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| − | ** {{decc|Alpha 21264}}
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| − | ** {{decc|StrongARM}}
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| − | * HAL
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| − | ** {{hal|SPARC64 II}}
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| − | * Fujitsu
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| − | ** {{fujitsu|TurboSPARC}}
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| − | * IBM
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| − | ** {{ibm|PowerPC 603ev}}
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| − | ** {{ibm|PowerPC 604}}
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| − | ** {{ibm|PowerPC 604e}}
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| − | ** {{ibm|PowerPC RS64-II}}
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| − | * Cyrix
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| − | ** {{Cyrix|6x86}}
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| − | * MIPS
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| − | ** {{mips|R5000}}
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| − | ** {{mips|R10000}}
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| − | ** {{mips|R4400}}
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| − | * Sun
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| − | ** {{sun|UltraSPARC II}}
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| − | ** {{sun|UltraSPARC IIi}}
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| − | * NEC
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| − | ** {{nec|VR4300}}
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| − | * Parallax
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| − | ** {{parallax|Propeller 1}}
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| − | {{expand list}}
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| − | | |
| − | == 350 nm Microcontrollers==
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| − | * AMD
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| − | ** {{amd|Am186Cx}}
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| − | ** {{amd|Am186Ex}}
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| − | {{expand list}}
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| − | | |
| − | == 350 nm Microarchitectures ==
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| − | * AMD
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| − | ** {{amd|K5|l=arch}}
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| − | ** {{amd|K6|l=arch}}
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| − | * Intel
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| − | ** {{intel|80186|l=arch}} (embedded [[IP cores]] only)
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| − | * DEC
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| − | ** {{decc|Alpha 21264|l=arch}}
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| − | ** {{decc|StrongARM|l=arch}}
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| − | {{expand list}}
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| − | | |
| − | == 350 nm Mikron ==
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| − | * МЦСТ <ref>http://www.mcst.ru/chips</ref>
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| − | ** МЦСТ-R150
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| − | | |
| − | == References ==
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| − | * Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
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| − | * von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722.
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| − | | |
| − | [[category:lithography]]
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