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<!-- TSMC --> | <!-- TSMC --> | ||
| process 1 fab = [[TSMC]] | | process 1 fab = [[TSMC]] | ||
− | | process 1 name = | + | | process 1 name = |
− | | process 1 date = | + | | process 1 date = |
− | | process 1 lith = | + | | process 1 lith = |
− | | process 1 immersion = | + | | process 1 immersion = |
− | | process 1 exposure = | + | | process 1 exposure = |
| process 1 wafer type = Bulk | | process 1 wafer type = Bulk | ||
| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
| process 1 transistor = Planar | | process 1 transistor = Planar | ||
− | | process 1 volt = | + | | process 1 volt = |
| process 1 layers = 10 | | process 1 layers = 10 | ||
| process 1 delta from = [[32 nm]] Δ | | process 1 delta from = [[32 nm]] Δ | ||
− | | process 1 gate len = | + | | process 1 gate len = |
| process 1 gate len Δ = | | process 1 gate len Δ = | ||
− | | process 1 cpp = | + | | process 1 cpp = |
| process 1 cpp Δ = | | process 1 cpp Δ = | ||
− | | process 1 mmp = | + | | process 1 mmp = |
| process 1 mmp Δ = | | process 1 mmp Δ = | ||
| process 1 sram hp = | | process 1 sram hp = | ||
| process 1 sram hp Δ = | | process 1 sram hp Δ = | ||
− | | process 1 sram hd = | + | | process 1 sram hd = |
| process 1 sram hd Δ = | | process 1 sram hd Δ = | ||
− | | process 1 sram lv = | + | | process 1 sram lv = |
| process 1 sram lv Δ = | | process 1 sram lv Δ = | ||
| process 1 dram = | | process 1 dram = | ||
| process 1 dram Δ = | | process 1 dram Δ = | ||
<!-- IBM --> | <!-- IBM --> | ||
− | | process 2 fab = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance | + | | process 2 fab = [[Common Platform Alliance ]]<info>The '''Common Platform Alliance '' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[NEC]], [[STMicroelectronics]], [[Infineon Technologies]], [[Chartered Semiconductor Manufacturing]]</info> |
− | | process 2 name = 28LP | + | | process 2 name = 28LP/28LPP/28SLP |
− | | process 2 date = | + | | process 2 date = 2 |
− | | process 2 lith = | + | | process 2 lith = |
− | | process 2 immersion = | + | | process 2 immersion = |
− | | process 2 exposure = | + | | process 2 exposure = |
| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
| process 2 wafer size = 300 mm | | process 2 wafer size = 300 mm | ||
| process 2 transistor = Planar | | process 2 transistor = Planar | ||
− | | process 2 volt = 1 | + | | process 2 volt = 1 V |
− | | process 2 layers = | + | | process 2 layers = |
| process 2 delta from = [[32 nm]] Δ | | process 2 delta from = [[32 nm]] Δ | ||
− | | process 2 gate len = | + | | process 2 gate len = |
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
| process 2 cpp = 113.4 nm | | process 2 cpp = 113.4 nm | ||
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| process 2 dram = | | process 2 dram = | ||
| process 2 dram Δ = | | process 2 dram Δ = | ||
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}} | }} | ||
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* AMD | * AMD | ||
** {{amd|A8}} | ** {{amd|A8}} | ||
− | ** {{amd|A10 | + | ** {{amd|A10}} |
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* Intel (Fab'ed by [[TSMC]]) | * Intel (Fab'ed by [[TSMC]]) | ||
** {{intel|Atom x3}} | ** {{intel|Atom x3}} | ||
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** {{pezy|PEZY-SC}} | ** {{pezy|PEZY-SC}} | ||
** {{pezy|PEZY-SCnp}} | ** {{pezy|PEZY-SCnp}} | ||
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* Xiaomi | * Xiaomi | ||
** {{xiaomi|Surge}} | ** {{xiaomi|Surge}} | ||
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* ARM Holdings | * ARM Holdings | ||
** {{armh|Cortex-A53|l=arch}} | ** {{armh|Cortex-A53|l=arch}} | ||
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* Phytium | * Phytium | ||
** {{phytium|Xiaomi|l=arch}} | ** {{phytium|Xiaomi|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
== References == | == References == | ||
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* Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009. | * Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009. | ||
* Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. | * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012. | ||
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* James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014. | * James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014. | ||
− | + | * [[:File:samsung foundry solution 28-32nm.pdf|Samsung foundry solution for 32 & 28 nm]] | |
− | [[ |