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{{lithography processes}} | {{lithography processes}} | ||
− | The ''' | + | The '''250 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[350 nm lithography process|350 nm process]] node. Commercial [[integrated circuit]] manufacturing using 250 nm process began in 1997 and was eventually replaced by [[180 nm]] by 1999. |
== Industry == | == Industry == | ||
− | The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 | + | The 0.25 µm-based process entered production at [[Intel]] in 1997. Intel original 0.25 micron process was named ''P856'' or ''Process 856''. A second process, named ''P856.5'', was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm<sup>2</sup>, 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon|polysilicon]] electode. It used [[wikipedia:Aluminium|Al]] inter-connects and an [[wikipedia:Silicon|Si]] channels. |
{{scrolling table/top|style=text-align: right; | first=Fab | {{scrolling table/top|style=text-align: right; | first=Fab | ||
|Process Name | |Process Name | ||
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|Contacted Gate Pitch | |Contacted Gate Pitch | ||
|Interconnect Pitch (M1P) | |Interconnect Pitch (M1P) | ||
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{{scrolling table/mid}} | {{scrolling table/mid}} | ||
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− | ! colspan=" | + | ! colspan="2" | [[Intel]] || colspan="2" | [[IBM]] || colspan="2" | [[AMD]] || colspan="2" | [[TI]] || colspan="2" | [[DEC]] || colspan="2" | [[IDT]] || colspan="2" | [[Fujitsu]] |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | P856 | + | | colspan="2" | P856 || colspan="2" | CMOS-6X || colspan="2" | CS-44 || colspan="2" | C07 || colspan="2" | CMOS-7 || colspan="2" | CMOS-10+ || colspan="2" | CS-70 |
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− | + | ! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ !! Value !! [[350 nm]] Δ | |
|- | |- | ||
− | | 500 nm || 0.91x || ? nm || ?x || ? nm || ?x | + | | 500 nm || 0.91x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
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− | | 640 nm || 0.72x | + | | 640 nm || 0.72x || 700 nm || ?x || 880 nm || ?x || 850 nm || ?x || 840 nm || ?x || 940 nm || ?x || 900 nm || ?x |
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− | | 10.26 | + | | 10.26 µm<sup>2</sup> || 0.57x || 8.6 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x || 10.5 µm<sup>2</sup> || ?x || 11.5 µm<sup>2</sup> || ?x || 11.2 µm<sup>2</sup> || ?x || ? µm<sup>2</sup> || ?x |
{{scrolling table/end}} | {{scrolling table/end}} | ||
=== Design Rules === | === Design Rules === | ||
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== 250 nm Microprocessors== | == 250 nm Microprocessors== | ||
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* Intel | * Intel | ||
** {{intel|Pentium MMX}}, 200-300 MHz September, 1997 | ** {{intel|Pentium MMX}}, 200-300 MHz September, 1997 | ||
** {{intel|Pentium II}}, 333-450 MHz, January 1998 | ** {{intel|Pentium II}}, 333-450 MHz, January 1998 | ||
− | ** {{intel| | + | ** {{intel|Pentium II}} Notebook, 233-300 MHz, April 1998 |
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** {{intel|Celeron}}, 200-300 MHz, April 1998 | ** {{intel|Celeron}}, 200-300 MHz, April 1998 | ||
** {{intel|Celeron}}, 300-533 MHz, August 1998 | ** {{intel|Celeron}}, 300-533 MHz, August 1998 | ||
** {{intel|Celeron}} Notebook, 266-466 MHz, January 1999 | ** {{intel|Celeron}} Notebook, 266-466 MHz, January 1999 | ||
** {{intel|Pentium III}}, 450-600 MHz, February 1999 | ** {{intel|Pentium III}}, 450-600 MHz, February 1999 | ||
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* MIPS | * MIPS | ||
** {{mips|R10000}}, 1997, fab'ed by NEC | ** {{mips|R10000}}, 1997, fab'ed by NEC | ||
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{{expand list}} | {{expand list}} | ||
== 250 nm Microarchitectures == | == 250 nm Microarchitectures == | ||
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{{expand list}} | {{expand list}} | ||
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