Editing 22 nm lithography process

{{lithography processes}}
The '''22 nanometer (22 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[28 nm lithography process|28 nm process]] stopgap. The term "22 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 22 nm process began in 2008 for memory and 2012 for [[MPU]]s. This technology was replaced by with [[20 nm lithography process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015.

== Industry ==
The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.


{{finfet nodes comp
<!-- Intel -->
 | process 1 fab          = [[Intel]]
 | process 1 name         = P1270 (CPU) / P1271 (SoC)
 | process 1 date         = 2011
 | process 1 lith         = 193 nm
 | process 1 immersion    = Yes
 | process 1 exposure     = [[SADP]]
 | process 1 wafer type   = Bulk
 | process 1 wafer size   = 300 mm
 | process 1 transistor   = FinFET
 | process 1 volt         = 0.75 V
 | process 1 delta from   = [[32 nm]] Δ
 | process 1 fin pitch    = 60 nm
 | process 1 fin pitch Δ  = -
 | process 1 fin width    = 8 nm
 | process 1 fin width Δ  = 
 | process 1 fin height   = 34 nm
 | process 1 fin height Δ = 
 | process 1 gate len     = 26 nm
 | process 1 gate len Δ   = 
 | process 1 cpp          = 90 nm
 | process 1 cpp Δ        = 0.80x
 | process 1 mmp          = 80 nm
 | process 1 mmp Δ        = 0.71x
 | process 1 sram hp      = 0.130 µm²
 | process 1 sram hp Δ    = &nbsp;
 | process 1 sram hd      = 0.092 µm²
 | process 1 sram hd Δ    = &nbsp;
 | process 1 sram lv      = 0.108 µm²
 | process 1 sram lv Δ    = &nbsp;
 | process 1 dram         = 0.029 µm²
 | process 1 dram Δ       = &nbsp;
<!-- Intel 22FFL -->
 | process 2 fab          = [[Intel]]
 | process 2 name         = 22FFL
 | process 2 date         = 2017
 | process 2 lith         = 193 nm
 | process 2 immersion    = Yes
 | process 2 exposure     = [[SADP]]
 | process 2 wafer type   = Bulk
 | process 2 wafer size   = 300 mm
 | process 2 transistor   = FinFET
 | process 2 volt         = &nbsp;
 | process 2 delta from   = [[32 nm]] Δ
 | process 2 fin pitch    = 45 nm
 | process 2 fin pitch Δ  = -
 | process 2 fin width    = &nbsp;
 | process 2 fin width Δ  = 
 | process 2 fin height   = &nbsp;
 | process 2 fin height Δ = 
 | process 2 gate len     = 30 nm
 | process 2 gate len Δ   = -
 | process 2 cpp          = 108 nm
 | process 2 cpp Δ        = -
 | process 2 mmp          = 90 nm
 | process 2 mmp Δ        = -
 | process 2 sram hp      = &nbsp;
 | process 2 sram hp Δ    = -
 | process 2 sram hd      = 0.088 µm²
 | process 2 sram hd Δ    = -
 | process 2 sram lv      = &nbsp;
 | process 2 sram lv Δ    = -
 | process 2 dram         = &nbsp;
 | process 2 dram Δ       = -
<!-- Samsung -->
 | process 3 fab          = [[IBM]]
 | process 3 name         = &nbsp;
 | process 3 date         = 2012
 | process 3 lith         = 193
 | process 3 immersion    = Yes
 | process 3 exposure     = &nbsp;
 | process 3 wafer type   = SOI
 | process 3 wafer size   = 300 mm
 | process 3 transistor   = Planar
 | process 3 volt         = &nbsp;
 | process 3 delta from   = [[32 nm]] Δ
 | process 3 fin pitch    = -
 | process 3 fin pitch Δ  = 
 | process 3 fin width    = 
 | process 3 fin width Δ  = 
 | process 3 fin height   = 
 | process 3 fin height Δ = 
 | process 3 gate len     = 
 | process 3 gate len Δ   = 
 | process 3 cpp          = 100 nm
 | process 3 cpp Δ        = 
 | process 3 mmp          = 80 nm
 | process 3 mmp Δ        = 
 | process 3 sram hp      = 0.144 µm²
 | process 3 sram hp Δ    = 
 | process 3 sram hd      = 0.128 µm²
 | process 3 sram hd Δ    = 
 | process 3 sram lv      = 
 | process 3 sram lv Δ    = 
 | process 3 dram         = 0.026 µm²
 | process 3 dram Δ       = 
}}

=== Intel ===
[[File:intel 22nm tri-gate transistors.png|650px]]
{| class="wikitable collapsible collapsed"
|-
! colspan="7" | Intel 22nm SoC Interconnect Design Rules
|-
! Layer !! Pitch !! Process !! Dielectric Materials !! [[CPU]] !! [[SoC]] || Image
|-
| Fin || 60 nm || - || - || Fin || Fin || rowspan="9" | [[File:intel 22nm rules.png]]
|-
| Contact || 90 nm || SAC || - || Contact || Contact
|-
| M1 || 90 nm || SAV || ULK CDO || M1 || M1
|-
| MT - 1x || 80 nm || SAV || ULK CDO || M2/M3 || 2-6 layers
|-
| MT - 1.4x || 112 nm || SAV || ULK CDO || M4 || Semi-global
|-
| MT - 2x || 160 nm || SAV || ULK CDO || M5 || Semi-global
|-
| MT - 3x || 240 nm || SAV || ULK CDO || M6 || Global Routing
|-
| MT - 4x || 320 nm<br>360 nm || Via First || LK CDO || M7/M8 || Global Routing
|-
| MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal
|}


{| class="wikitable collapsible collapsed"
|-
! colspan="7" | Intel 22nm SoC Transistor Characteristics
|-
! Transistor Type !! colspan="2" | High Speed Logic !! colspan="2" | Low Power Logic !! colspan="2" | High Voltage Logic
|-
| Options || High Performance (HP) || Standard Perf/Power (SP) || Low Power (LP) || Ultra-Low Power (ULP) || 1.8 V || 3.3 V
|-
| V<sub>dd</sub> (V) || 0.7 V / 1 V || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1.2 V || 1.5 V / 1.8 V / 3.3 V || 3.3 V / >5V
|-
| Gate Pitch (nm) || 90 || 90 || 90 || 108 || min. 180 || min 450
|-
| L<sub>gate</sub> (nm) || 30 || 34 || 34 || 40 || min. 80 || in 280 
|-
| N/PMOS Idsat/Ioff (mA/µm) || 1.08/0.91 @ 0.75 V, 100 nA/µm || 0.71/0.59 @0.75 V, 1 nA/µm || 0.41/0.37 @ 0.75 V, 30 pA/µm || 0.35/0.33 @ 0.75 V, 15 pA/µm || 0.92/0.8 @ 1.8 V, 10 pA/µm || 1/0.8 @ 3.3 V, 10 pA/µm
|}

== Find models ==
{{#ask:
 [[instance of::microprocessor]]
 [[process::22 nm]]
 | ?full page name
 | ?name
 | ?microprocessor family
 | ?microarchitecture
 | ?process
 | ?designer
 | ?manufacturer
 | ?first launched
 | ?base frequency
 | format=template|link=all|sort=name|order=asc|headers=hide|mainlabel=-|intro=<table class="wikitable"><tr><th colspan="8">[[22 nm]] Microprocessors</th></tr><tr><th colspan="3">Model</th><th colspan="5">Specs</th></tr><tr><th>Model</th><th>Family</th><th>µarch</th><th>Process</th><th>Designer</th><th>Manufacturer</th><th>Intro</th><th>Freq</th></tr>|outro=</table>|limit=0|searchlabel=Click to browse all 22 nm MPU models|sep=,|template=proc table 1|userparam=9
}}

== 22 nm Microprocessors==
* Intel
** {{intel|Core i3}}
** {{intel|Core i5}}
** {{intel|Core i7}}
** {{intel|Core i7EE}}
** {{intel|Xeon}}
** {{intel|Xeon E3}}
** {{intel|Xeon E5}}
** {{intel|Xeon E7}}
{{expand list}}


{{#ask:
 [[instance of::microprocessor]]
 [[process::22 nm]]
 | ?name
 | ?process
 | ?manufacturer
 | ?microprocessor family
 | format=broadtable
 | limit=0
 | sep=,
 | searchlabel=Click to browse all 22 nm MPU models
}}

== 22 nm Microarchitectures==
* Intel:
** {{intel|Haswell}}
** {{intel|Ivy Bridge}}
** {{intel|Silvermont}}

{{expand list}}

== Documents ==
* [[:File:22FFL-2017.pdf|Intel's 22FFL technology]]

== References ==
* Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.
* Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
* Hamzaoglu, Fatih, et al. "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014.


[[Category:Lithography]]