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The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry. | The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry. | ||
− | + | {{scrolling table/top|style=text-align: right; | first=Fab | |
− | {{ | + | |Process Name |
− | + | |1st Production | |
− | + | |Transistor | |
− | + | |Wafer | |
− | + | | | |
− | + | |Fin Pitch | |
− | + | |Fin Width | |
− | + | |Fin Height | |
− | + | |Gate Length | |
− | + | |Contacted Gate Pitch | |
− | + | |Interconnect Pitch (M1P) | |
− | + | |SRAM bit cell (HP) | |
− | + | |SRAM bit cell (HD) | |
− | + | |DRAM bit cell | |
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}} | }} | ||
− | + | {{scrolling table/mid}} | |
+ | |- | ||
+ | ! colspan="4" | [[Intel]] !! colspan="2" | Common Platform<info>[[IBM]] / [[GlobalFoundries]] / [[AMD]] / [[Freescale]] / [[STMicroelectronics]] / [[Toshiba]] / CNSE</info> | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | P1270 (CPU) / P1271 (SoC) || colspan="2" | 22FFL || colspan="2" | | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="4" | FinFET || colspan="2" | Planar | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="2" | 2011 || colspan="2" | 2017 || colspan="2" | 2012 | ||
+ | |- style="text-align: center;" | ||
+ | | colspan="8" | 300 mm | ||
+ | |- | ||
+ | ! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ | ||
+ | |- | ||
+ | | 60 nm || rowspan="3" style="text-align: center;" | N/A || 45 nm || rowspan="9" style="text-align: center;" | N/A || colspan="2" rowspan="3" style="text-align: center;" | N/A | ||
+ | |- | ||
+ | | 8 nm || ? nm | ||
+ | |- | ||
+ | | 34 nm || ? nm | ||
+ | |- | ||
+ | | 26 nm || || 30 nm || || | ||
+ | |- | ||
+ | | 90 nm || 0.80x || 108 nm || 100 nm || 0.79x | ||
+ | |- | ||
+ | | 80 nm || 0.71x || 90 nm || 80 nm || ?x | ||
+ | |- | ||
+ | | 0.1080 µm² || 0.63x || ? µm² || 0.1 µm² || 0.67x | ||
+ | |- | ||
+ | | 0.092 µm² || ?x || 0.88 µm² || ? µm² || ?x | ||
+ | |- | ||
+ | | 0.029 µm² || || || 0.026 µm² || 0.67x | ||
+ | {{scrolling table/end}} | ||
=== Intel === | === Intel === | ||
[[File:intel 22nm tri-gate transistors.png|650px]] | [[File:intel 22nm tri-gate transistors.png|650px]] | ||
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== 22 nm Microarchitectures== | == 22 nm Microarchitectures== | ||
− | * Intel | + | * Intel: |
− | ** {{intel|Haswell | + | ** {{intel|Haswell}} |
− | ** {{intel|Ivy Bridge | + | ** {{intel|Ivy Bridge}} |
− | ** {{intel|Silvermont | + | ** {{intel|Silvermont}} |
− | + | ||
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{{expand list}} | {{expand list}} | ||
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== References == | == References == | ||
− | * IEDM 2012 | + | * Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012. |
− | * IEDM 2014 | + | * Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014. |
− | * ISSCC | + | * Hamzaoglu, Fatih, et al. "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014. |
+ | |||
− | [[ | + | [[Category:Lithography]] |