From WikiChip
Editing 22 nm lithography process

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 3: Line 3:
  
 
== Industry ==
 
== Industry ==
−
The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.
+
The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. Those transistors were not used in IBM's process
  
−
 
+
{{scrolling table/top|style=text-align: right; | first=Fab
−
{{finfet nodes comp
+
  |Process Name
−
<!-- Intel -->
+
  |1st Production
−
| process 1 fab          = [[Intel]]
+
  |Wafer
−
| process 1 name        = P1270 (CPU) / P1271 (SoC)
+
  |&nbsp;
−
| process 1 date        = 2011
+
  |Fin Pitch
−
| process 1 lith        = 193 nm
+
  |Fin Width
−
| process 1 immersion    = Yes
+
  |Fin Height
−
| process 1 exposure    = [[SADP]]
+
  |Contacted Gate Pitch
−
| process 1 wafer type  = Bulk
+
  |Interconnect Pitch (M1P)
−
| process 1 wafer size  = 300 mm
+
  |SRAM bit cell (HP)
−
| process 1 transistor  = FinFET
+
  |SRAM bit cell (HD)
−
| process 1 volt        = 0.75 V
+
  |DRAM bit cell
−
| process 1 delta from  = [[32 nm]] Δ
 
−
| process 1 fin pitch    = 60 nm
 
−
| process 1 fin pitch Δ  = -
 
−
| process 1 fin width    = 8 nm
 
−
| process 1 fin width Δ  =
 
−
| process 1 fin height  = 34 nm
 
−
| process 1 fin height Δ =
 
−
| process 1 gate len    = 26 nm
 
−
| process 1 gate len Δ  =
 
−
| process 1 cpp          = 90 nm
 
−
| process 1 cpp Δ        = 0.80x
 
−
| process 1 mmp          = 80 nm
 
−
| process 1 mmp Δ        = 0.71x
 
−
| process 1 sram hp      = 0.130 µm²
 
−
| process 1 sram hp Δ    = 0.65x
 
−
| process 1 sram hd      = 0.092 µm²
 
−
| process 1 sram hd Δ    = 0.62x
 
−
| process 1 sram lv      = 0.108 µm²
 
−
| process 1 sram lv Δ    = 0.63x
 
−
| process 1 dram        = 0.029 µm²
 
−
| process 1 dram Δ      = &nbsp;
 
−
<!-- Intel 22FFL -->
 
−
| process 2 fab          = [[Intel]]
 
−
| process 2 name        = 22FFL (P1222)
 
−
  | process 2 date        = 2017
 
−
  | process 2 lith        = 193 nm
 
−
  | process 2 immersion    = Yes
 
−
  | process 2 exposure    = [[SADP]]
 
−
| process 2 wafer type  = Bulk
 
−
| process 2 wafer size  = 300 mm
 
−
| process 2 transistor  = FinFET
 
−
| process 2 volt        = 0.7 V
 
−
| process 2 delta from  = [[32 nm]] Δ
 
−
| process 2 fin pitch    = 45 nm
 
−
| process 2 fin pitch Δ  = -
 
−
| process 2 fin width    = &nbsp;
 
−
  | process 2 fin width Δ  =
 
−
  | process 2 fin height  = &nbsp;
 
−
  | process 2 fin height Δ =
 
−
  | process 2 gate len    = 30 nm
 
−
  | process 2 gate len Δ  = -
 
−
  | process 2 cpp          = 108 nm
 
−
  | process 2 cpp Δ        = -
 
−
| process 2 mmp          = 90 nm
 
−
| process 2 mmp Δ        = -
 
−
  | process 2 sram hp      = &nbsp;
 
−
| process 2 sram hp Δ    = -
 
−
| process 2 sram hd      = 0.088 µm²
 
−
| process 2 sram hd Δ    = -
 
−
| process 2 sram lv      = &nbsp;
 
−
| process 2 sram lv Δ    = -
 
−
| process 2 dram        = &nbsp;
 
−
| process 2 dram Δ      = -
 
−
<!-- Samsung -->
 
−
| process 3 fab          = [[IBM]]
 
−
| process 3 name        = 22HP
 
−
| process 3 date        = 2013
 
−
| process 3 lith        = 193
 
−
| process 3 immersion    = Yes
 
−
| process 3 exposure    = &nbsp;
 
−
| process 3 wafer type  = SOI
 
−
| process 3 wafer size  = 300 mm
 
−
| process 3 transistor  = Planar
 
−
| process 3 volt        = 0.75 V
 
−
| process 3 delta from  = [[32 nm]] Δ
 
−
| process 3 fin pitch    = -
 
−
| process 3 fin pitch Δ  =
 
−
| process 3 fin width    =
 
−
| process 3 fin width Δ  =
 
−
| process 3 fin height  =
 
−
| process 3 fin height Δ =
 
−
| process 3 gate len    = 25-33 nm
 
−
| process 3 gate len Δ  = 0.83-1.1x
 
−
| process 3 cpp          = 100 nm
 
−
| process 3 cpp Δ        = 0.79x
 
−
| process 3 mmp          = 80 nm
 
−
| process 3 mmp Δ        = 0.80x
 
−
| process 3 sram hp      = 0.144 µm²
 
−
| process 3 sram hp Δ    = &nbsp;
 
−
| process 3 sram hd      = 0.128 µm²
 
−
| process 3 sram hd Δ    = 0.86x
 
−
| process 3 sram lv      = &nbsp;
 
−
| process 3 sram lv Δ    = &nbsp;
 
−
| process 3 dram        = 0.026 µm²
 
−
| process 3 dram Δ      = 0.67x
 
 
}}
 
}}
−
 
+
{{scrolling table/mid}}
−
=== Intel ===
+
|-
−
[[File:intel 22nm tri-gate transistors.png|650px]]
+
! colspan="2" | [[Intel]] !! colspan="2" | Common Platform<info>[[IBM]] / [[GlobalFoundries]] / [[AMD]] / [[Freescale]] / [[STMicroelectronics]] / [[Toshiba]] / CNSE</info>
 +
|- style="text-align: center;"
 +
| colspan="2" | P1270 || colspan="2" |
 +
|- style="text-align: center;"
 +
| colspan="2" | 2011 || colspan="2" | 2012
 +
|- style="text-align: center;"
 +
| colspan="6" | 300mm
 +
|-
 +
! Value !! [[32 nm]] Δ !! Value !! [[32 nm]] Δ
 +
|-
 +
| 60 nm || colspan="3" rowspan="3" style="text-align: center;" | N/A
 +
|-
 +
| 32 nm
 +
|-
 +
| 8 nm
 +
|-
 +
| 90 nm || 0.80x || 100 nm || 0.79x
 +
|-
 +
| 80 nm || 0.71x || 80 nm || ?x
 +
|-
 +
| 0.1080 µm<sup>2</sup> || 0.63x || 0.1 µm<sup>2</sup>  || 0.67x
 +
|-
 +
| 0.092 µm<sup>2</sup> || ?x
 +
|-
 +
| || || 0.026 µm<sup>2</sup> || 0.67x
 +
{{scrolling table/end}}
 +
=== Design Rules ===
 
{| class="wikitable collapsible collapsed"
 
{| class="wikitable collapsible collapsed"
 
|-
 
|-
−
! colspan="7" | Intel 22nm SoC Interconnect Design Rules
+
! colspan="6" | Intel 22nm SoC Interconnect Design Rules
 
|-
 
|-
−
! Layer !! Pitch !! Process !! Dielectric Materials !! [[CPU]] !! [[SoC]] || Image
+
! Layer !! Pitch !! Process !! Dielectric Materials !! [[CPU]] !! [[SoC]]
 
|-
 
|-
−
| Fin || 60 nm || - || - || Fin || Fin || rowspan="9" | [[File:intel 22nm rules.png]]
+
| Fin || 60 nm || - || - || Fin || Fin
 
|-
 
|-
 
| Contact || 90 nm || SAC || - || Contact || Contact
 
| Contact || 90 nm || SAC || - || Contact || Contact
Line 131: Line 72:
 
| MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal
 
| MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal
 
|}
 
|}
−
 
−
 
−
{| class="wikitable collapsible collapsed"
 
−
|-
 
−
! colspan="7" | Intel 22nm SoC Transistor Characteristics
 
−
|-
 
−
! Transistor Type !! colspan="2" | High Speed Logic !! colspan="2" | Low Power Logic !! colspan="2" | High Voltage Logic
 
−
|-
 
−
| Options || High Performance (HP) || Standard Perf/Power (SP) || Low Power (LP) || Ultra-Low Power (ULP) || 1.8 V || 3.3 V
 
−
|-
 
−
| V<sub>dd</sub> (V) || 0.7 V / 1 V || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1.2 V || 1.5 V / 1.8 V / 3.3 V || 3.3 V / >5V
 
−
|-
 
−
| Gate Pitch (nm) || 90 || 90 || 90 || 108 || min. 180 || min 450
 
−
|-
 
−
| L<sub>gate</sub> (nm) || 30 || 34 || 34 || 40 || min. 80 || in 280
 
−
|-
 
−
| N/PMOS Idsat/Ioff (mA/µm) || 1.08/0.91 @ 0.75 V, 100 nA/µm || 0.71/0.59 @0.75 V, 1 nA/µm || 0.41/0.37 @ 0.75 V, 30 pA/µm || 0.35/0.33 @ 0.75 V, 15 pA/µm || 0.92/0.8 @ 1.8 V, 10 pA/µm || 1/0.8 @ 3.3 V, 10 pA/µm
 
−
|}
 
−
 
 
== Find models ==
 
== Find models ==
 
{{#ask:
 
{{#ask:
Line 191: Line 113:
 
  | searchlabel=Click to browse all 22 nm MPU models
 
  | searchlabel=Click to browse all 22 nm MPU models
 
}}
 
}}
 +
 +
== 22 nm System on Chips==
 +
{{expand list}}
  
 
== 22 nm Microarchitectures==
 
== 22 nm Microarchitectures==
−
* Intel
+
* Intel:
−
** {{intel|Haswell|l=arch}}
+
** {{intel|Haswell}}
−
** {{intel|Ivy Bridge|l=arch}}
+
** {{intel|Ivy Bridge}}
−
** {{intel|Silvermont|l=arch}}
+
** {{intel|Silvermont}}
−
* IBM
+
 
−
** {{ibm|POWER8|l=arch}}
 
−
** {{ibm|z13|l=arch}}
 
 
{{expand list}}
 
{{expand list}}
  
−
== Documents ==
 
−
* [[:File:22FFL-2017.pdf|Intel's 22FFL technology]]
 
−
 
−
== References ==
 
−
* IEDM 2012
 
−
* IEDM 2014
 
−
* ISSCC 2015
 
  
−
[[category:lithography]]
+
[[Category:Lithography]]

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/22_nm_lithography_process"