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| {{lithography processes}} | | {{lithography processes}} |
− | The '''22 nanometer (22 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[28 nm lithography process|28 nm process]] stopgap. The term "22 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 22 nm process began in 2008 for memory and 2012 for [[MPU]]s. This technology was replaced by with [[20 nm lithography process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015. | + | The '''22 nm lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[28 nm lithography process|28 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 22 nm process began in 2008 for memory and 2012 for [[MPU]]s. This technology was replaced by with [[20 nm lithography process|20 nm process]] (HN) in 2014 and [[16 nm lithography process|16 nm process]] (FN) in late 2015. |
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| == Industry == | | == Industry == |
− | The 22 nm became Intel's first generation of Tri-gate [[FinFET]] transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.
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− | {{finfet nodes comp
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− | <!-- Intel -->
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− | | process 1 fab = [[Intel]]
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− | | process 1 name = P1270 (CPU) / P1271 (SoC)
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− | | process 1 date = 2011
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− | | process 1 lith = 193 nm
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− | | process 1 immersion = Yes
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− | | process 1 exposure = [[SADP]]
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− | | process 1 wafer type = Bulk
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− | | process 1 wafer size = 300 mm
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− | | process 1 transistor = FinFET
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− | | process 1 volt = 0.75 V
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− | | process 1 delta from = [[32 nm]] Δ
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− | | process 1 fin pitch = 60 nm
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− | | process 1 fin pitch Δ = -
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− | | process 1 fin width = 8 nm
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− | | process 1 fin width Δ =
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− | | process 1 fin height = 34 nm
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− | | process 1 fin height Δ =
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− | | process 1 gate len = 26 nm
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− | | process 1 gate len Δ =
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− | | process 1 cpp = 90 nm
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− | | process 1 cpp Δ = 0.80x
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− | | process 1 mmp = 80 nm
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− | | process 1 mmp Δ = 0.71x
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− | | process 1 sram hp = 0.130 µm²
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− | | process 1 sram hp Δ = 0.65x
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− | | process 1 sram hd = 0.092 µm²
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− | | process 1 sram hd Δ = 0.62x
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− | | process 1 sram lv = 0.108 µm²
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− | | process 1 sram lv Δ = 0.63x
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− | | process 1 dram = 0.029 µm²
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− | | process 1 dram Δ =
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− | <!-- Intel 22FFL -->
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− | | process 2 fab = [[Intel]]
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− | | process 2 name = 22FFL (P1222)
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− | | process 2 date = 2017
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− | | process 2 lith = 193 nm
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− | | process 2 immersion = Yes
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− | | process 2 exposure = [[SADP]]
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− | | process 2 wafer type = Bulk
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− | | process 2 wafer size = 300 mm
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− | | process 2 transistor = FinFET
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− | | process 2 volt = 0.7 V
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− | | process 2 delta from = [[32 nm]] Δ
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− | | process 2 fin pitch = 45 nm
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− | | process 2 fin pitch Δ = -
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− | | process 2 fin width =
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− | | process 2 fin width Δ =
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− | | process 2 fin height =
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− | | process 2 fin height Δ =
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− | | process 2 gate len = 30 nm
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− | | process 2 gate len Δ = -
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− | | process 2 cpp = 108 nm
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− | | process 2 cpp Δ = -
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− | | process 2 mmp = 90 nm
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− | | process 2 mmp Δ = -
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− | | process 2 sram hp =
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− | | process 2 sram hp Δ = -
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− | | process 2 sram hd = 0.088 µm²
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− | | process 2 sram hd Δ = -
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− | | process 2 sram lv =
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− | | process 2 sram lv Δ = -
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− | | process 2 dram =
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− | | process 2 dram Δ = -
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− | <!-- Samsung -->
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− | | process 3 fab = [[IBM]]
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− | | process 3 name = 22HP
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− | | process 3 date = 2013
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− | | process 3 lith = 193
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− | | process 3 immersion = Yes
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− | | process 3 exposure =
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− | | process 3 wafer type = SOI
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− | | process 3 wafer size = 300 mm
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− | | process 3 transistor = Planar
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− | | process 3 volt = 0.75 V
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− | | process 3 delta from = [[32 nm]] Δ
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− | | process 3 fin pitch = -
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− | | process 3 fin pitch Δ =
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− | | process 3 fin width =
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− | | process 3 fin width Δ =
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− | | process 3 fin height =
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− | | process 3 fin height Δ =
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− | | process 3 gate len = 25-33 nm
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− | | process 3 gate len Δ = 0.83-1.1x
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− | | process 3 cpp = 100 nm
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− | | process 3 cpp Δ = 0.79x
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− | | process 3 mmp = 80 nm
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− | | process 3 mmp Δ = 0.80x
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− | | process 3 sram hp = 0.144 µm²
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− | | process 3 sram hp Δ =
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− | | process 3 sram hd = 0.128 µm²
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− | | process 3 sram hd Δ = 0.86x
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− | | process 3 sram lv =
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− | | process 3 sram lv Δ =
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− | | process 3 dram = 0.026 µm²
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− | | process 3 dram Δ = 0.67x
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− | }}
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| === Intel === | | === Intel === |
− | [[File:intel 22nm tri-gate transistors.png|650px]] | + | 22 nm was Intel's first generation of Tri-gate [[FinFET]] transistors. |
− | {| class="wikitable collapsible collapsed" | + | {| class="wikitable" |
| + | |- |
| + | | || Measurement || Scaling from [[32 nm]] |
| |- | | |- |
− | ! colspan="7" | Intel 22nm SoC Interconnect Design Rules
| + | | Fin Pitch || 60 nm || |
| |- | | |- |
− | ! Layer !! Pitch !! Process !! Dielectric Materials !! [[CPU]] !! [[SoC]] || Image
| + | | Contacted Gate Pitch || 90 nm || 0.80x |
| |- | | |- |
− | | Fin || 60 nm || - || - || Fin || Fin || rowspan="9" | [[File:intel 22nm rules.png]] | + | | Interconnect Pitch (M1P) || 80 nm || 0.71x |
| + | |- |
| + | | [[SRAM]] bit cell || 0.1080 µm<sup>2</sup> || High Performance |
| + | |- |
| + | | [[SRAM]] bit cell || 0.092 µm<sup>2</sup> || High Density |
| + | |} |
| + | |
| + | {| class="wikitable" |
| + | ! colspan="6" | SoC Interconnect Design Rules |
| + | |- |
| + | ! Layer !! Pitch !! Process !! Dielectric Materials !! [[CPU]] !! [[SoC]] |
| + | |- |
| + | | Fin || 60 nm || - || - || Fin || Fin |
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| | Contact || 90 nm || SAC || - || Contact || Contact | | | Contact || 90 nm || SAC || - || Contact || Contact |
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| | MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal | | | MT - TOP || 14 µm || Plate Up || Polymer || M9 || Top Metal |
| |} | | |} |
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− | {| class="wikitable collapsible collapsed"
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− | |-
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− | ! colspan="7" | Intel 22nm SoC Transistor Characteristics
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− | |-
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− | ! Transistor Type !! colspan="2" | High Speed Logic !! colspan="2" | Low Power Logic !! colspan="2" | High Voltage Logic
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− | |-
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− | | Options || High Performance (HP) || Standard Perf/Power (SP) || Low Power (LP) || Ultra-Low Power (ULP) || 1.8 V || 3.3 V
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− | |-
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− | | V<sub>dd</sub> (V) || 0.7 V / 1 V || 0.75 V / 1 V || 0.75 V / 1 V || 0.75 V / 1.2 V || 1.5 V / 1.8 V / 3.3 V || 3.3 V / >5V
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− | |-
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− | | Gate Pitch (nm) || 90 || 90 || 90 || 108 || min. 180 || min 450
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− | |-
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− | | L<sub>gate</sub> (nm) || 30 || 34 || 34 || 40 || min. 80 || in 280
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− | |-
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− | | N/PMOS Idsat/Ioff (mA/µm) || 1.08/0.91 @ 0.75 V, 100 nA/µm || 0.71/0.59 @0.75 V, 1 nA/µm || 0.41/0.37 @ 0.75 V, 30 pA/µm || 0.35/0.33 @ 0.75 V, 15 pA/µm || 0.92/0.8 @ 1.8 V, 10 pA/µm || 1/0.8 @ 3.3 V, 10 pA/µm
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− | |}
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− | == Find models ==
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− | {{#ask:
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− | [[instance of::microprocessor]]
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− | [[process::22 nm]]
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− | | ?full page name
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− | | ?name
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− | | ?microprocessor family
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− | | ?microarchitecture
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− | | ?process
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− | | ?designer
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− | | ?manufacturer
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− | | ?first launched
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− | | ?base frequency
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− | | format=template|link=all|sort=name|order=asc|headers=hide|mainlabel=-|intro=<table class="wikitable"><tr><th colspan="8">[[22 nm]] Microprocessors</th></tr><tr><th colspan="3">Model</th><th colspan="5">Specs</th></tr><tr><th>Model</th><th>Family</th><th>µarch</th><th>Process</th><th>Designer</th><th>Manufacturer</th><th>Intro</th><th>Freq</th></tr>|outro=</table>|limit=0|searchlabel=Click to browse all 22 nm MPU models|sep=,|template=proc table 1|userparam=9
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− | }}
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| == 22 nm Microprocessors== | | == 22 nm Microprocessors== |
| * Intel | | * Intel |
− | ** {{intel|Core i3}}
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− | ** {{intel|Core i5}}
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− | ** {{intel|Core i7}}
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| ** {{intel|Core i7EE}} | | ** {{intel|Core i7EE}} |
− | ** {{intel|Xeon}}
| + | |
− | ** {{intel|Xeon E3}}
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− | ** {{intel|Xeon E5}}
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− | ** {{intel|Xeon E7}}
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| {{expand list}} | | {{expand list}} |
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| + | == 22 nm System on Chips== |
| + | {{expand list}} |
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− | {{#ask:
| + | == 22 nm Microarchitectures== |
− | [[instance of::microprocessor]]
| + | * Intel: |
− | [[process::22 nm]]
| + | ** {{intel|Haswell}} |
− | | ?name
| + | ** {{intel|Ivy Bridge}} |
− | | ?process
| + | ** {{intel|Silvermont}} |
− | | ?manufacturer
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− | | ?microprocessor family
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− | | format=broadtable
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− | | limit=0
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− | | sep=,
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− | | searchlabel=Click to browse all 22 nm MPU models
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− | }} | |
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− | == 22 nm Microarchitectures==
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− | * Intel
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− | ** {{intel|Haswell|l=arch}}
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− | ** {{intel|Ivy Bridge|l=arch}}
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− | ** {{intel|Silvermont|l=arch}}
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− | * IBM
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− | ** {{ibm|POWER8|l=arch}}
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− | ** {{ibm|z13|l=arch}}
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| {{expand list}} | | {{expand list}} |
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− | == Documents ==
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− | * [[:File:22FFL-2017.pdf|Intel's 22FFL technology]]
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− |
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− | == References ==
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− | * IEDM 2012
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− | * IEDM 2014
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− | * ISSCC 2015
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− | [[category:lithography]] | + | [[Category:Lithography]] |