Editing 20 nm lithography process

{{lithography processes}}
The '''20 nanometer (20 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[22 nm lithography process|22 nm]] and [[16 nm lithography process|16 nm]] processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 20 nm process began in 2014. This technology superseded by commercial [[16 nm lithography process|16 nm process]].

== Industry ==
{{scrolling table/top|style=text-align: right; | first=Fab
 |Process Name
 |Transistor
 |Wafer
 |Metal Layers
 |&nbsp;
 |Contacted Gate Pitch
 |Interconnect Pitch (M1P)
 |SRAM bit cell
}}
{{scrolling table/mid}}
|-
! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]]
|- style="text-align: center;"
| colspan="2" | 20LPM || colspan="2" | &nbsp;
|- style="text-align: center;"
| colspan="4" | Planar
|- style="text-align: center;"
| colspan="4" | 300 mm
|- style="text-align: center;"
| colspan="2" | &nbsp; || colspan="2" | 10
|-
! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ
|-
| 86 nm || 0.75x || 90 nm || 0.77x
|-
| 64 nm || 0.71x || 64 nm || 0.67x
|-
| 0.081 µm² || 0.675x || 0.081 µm² || 0.64x
{{scrolling table/end}}

=== TSMC ===
TSMC demonstrated their 112 Mebibit [[SRAM]] wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.
{| class="collapsible collapsed wikitable"
|-
! colspan="2" | TSMC 112 Mib SRAM demo 20 nm wafer
|-
|
<table class="wikitable">
<tr><th>Technology</th><td>20 nm HK-MG</td></tr>
<tr><th>Metal scheme</th><td>1 Poly  / 7 Metal</td></tr>
<tr><th>Supply voltage</th><td>0.95 V (core)<br>1.8 V (i/o)</td></tr>
<tr><th>Bit cell size</th><td>0.081 µm²</td></tr>
<tr><th>macro configs</th><td>2048x134 MUX4</td></tr>
<tr><th>Capacity</th><td>112 Mib</td></tr>
<tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
<tr><th>Die Size</th><td>6400 µm x 6300 µm = 40.32 mm²</td></tr>
</table>
| [[File:tsmc 20nm SRAM block.png|400px]]
|}

== 20 nm Microprocessors==
* MediaTek
** {{mediatek|Helio}}
{{expand list}}

== 20 nm Microarchitectures==
{{expand list}}

== References ==
* Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.
* Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.

[[Category:Lithography]]
@@ Line 3: / Line 3: @@
 == Industry ==
-{{nodes comp
+{{scrolling table/top|style=text-align: right; | first=Fab
-<!-- TSMC -->
+  |Process Name
- | process 1 fab          = [[TSMC]]
+  |Transistor
- | process 1 name         = &nbsp;
+  |Wafer
- | process 1 date         = 3Q 2014
+  |Metal Layers
- | process 1 lith         = 193 nm
+  |&nbsp;
- | process 1 immersion    = Yes
+  |Contacted Gate Pitch
- | process 1 exposure     = &nbsp;
+  |Interconnect Pitch (M1P)
- | process 1 wafer type   = Bulk
+  |SRAM bit cell
- | process 1 wafer size   = 300 mm
- | process 1 transistor   = Planar
- | process 1 volt         = 0.95 V
- | process 1 layers       = 10
- | process 1 delta from   = [[28 nm]] Δ
- | process 1 gate len     = &nbsp;
- | process 1 gate len Δ   = &nbsp;
- | process 1 cpp          = 90 nm
- | process 1 cpp Δ        = 0.77x
- | process 1 mmp          = 64 nm
- | process 1 mmp Δ        = 0.67x
- | process 1 sram hp      = &nbsp;
- | process 1 sram hp Δ    = &nbsp;
- | process 1 sram hd      = 0.081 µm²
- | process 1 sram hd Δ    = 0.64x
- | process 1 sram lv      = &nbsp;
- | process 1 sram lv Δ    = &nbsp;
- | process 1 dram         = &nbsp;
- | process 1 dram Δ       = &nbsp;
-<!-- IBM -->
- | process 2 fab          = [[Common Platform Alliance]] <info>The '''Common Platform Alliance''' 20 nm node was a collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[STMicroelectronics]]</info>
- | process 2 name         = &nbsp;
- | process 2 date         = 2014
- | process 2 lith         = 193 nm
- | process 2 immersion    = Yes
- | process 2 exposure     = &nbsp;
- | process 2 wafer type   = Bulk
- | process 2 wafer size   = 300 mm
- | process 2 transistor   = Planar
- | process 2 volt         = 0.9 V
- | process 2 layers       = &nbsp;
- | process 2 delta from   = [[28 nm]] Δ
- | process 2 gate len     = 20 nm
- | process 2 gate len Δ   = 0.67x
- | process 2 cpp          = 86 nm
- | process 2 cpp Δ        = 0.76
- | process 2 mmp          = 64 nm
-  | process 2 mmp Δ        = 0.71x
-  | process 2 sram hp      = 0.102 µm²
- | process 2 sram hp Δ    = &nbsp;
-  | process 2 sram hd      = 0.081 µm²
-  | process 2 sram hd Δ    = 0.68x
-  | process 2 sram lv      = &nbsp;
-  | process 2 sram lv Δ    = &nbsp;
-  | process 2 dram         = &nbsp;
-  | process 2 dram Δ       = &nbsp;
 }}
+{{scrolling table/mid}}
+|-
+! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]]
+|- style="text-align: center;"
+| colspan="2" | 20LPM || colspan="2" | &nbsp;
+|- style="text-align: center;"
+| colspan="4" | Planar
+|- style="text-align: center;"
+| colspan="4" | 300 mm
+|- style="text-align: center;"
+| colspan="2" | &nbsp; || colspan="2" | 10
+|-
+! Value !! [[28 nm]] Δ !! Value !! [[28 nm]] Δ
+|-
+| 86 nm || 0.75x || 90 nm || 0.77x
+|-
+| 64 nm || 0.71x || 64 nm || 0.67x
+|-
+| 0.081 µm² || 0.675x || 0.081 µm² || 0.64x
+{{scrolling table/end}}
 === TSMC ===
@@ Line 83: / Line 57: @@
 * MediaTek
 ** {{mediatek|Helio}}
-* Fujitsu
-** {{fujitsu|SPARC64}}
-* Oracle
-** {{oracle|SPARC M8}}
 {{expand list}}
@@ Line 96: / Line 66: @@
 * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
-[[category:lithography]]
+[[Category:Lithography]]