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| {{lithography processes}} | | {{lithography processes}} |
− | The '''20 nanometer (20 nm) lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[22 nm lithography process|22 nm]] and [[16 nm lithography process|16 nm]] processes. The term "20 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial [[integrated circuit]] manufacturing using 20 nm process began in 2014. This technology superseded by commercial [[16 nm lithography process|16 nm process]]. | + | The '''20 nm lithography process''' is a [[technology node#half node|half-node]] semiconductor manufacturing process used as a stopgap between the [[22 nm lithography process|22 nm]] and [[16 nm lithography process|16 nm]] processes. Commercial [[integrated circuit]] manufacturing using 20 nm process began in 2014. This technology superseded by commercial [[16 nm lithography process|16 nm process]]. |
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− | == Industry == | + | == 20 nm Microprocessors== |
− | {{nodes comp | + | {{expand list}} |
− | <!-- TSMC -->
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− | | process 1 fab = [[TSMC]]
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− | | process 1 name =
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− | | process 1 date = 3Q 2014
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− | | process 1 lith = 193 nm
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− | | process 1 immersion = Yes
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− | | process 1 exposure =
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− | | process 1 wafer type = Bulk
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− | | process 1 wafer size = 300 mm
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− | | process 1 transistor = Planar
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− | | process 1 volt = 0.95 V
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− | | process 1 layers = 10
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− | | process 1 delta from = [[28 nm]] Δ
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− | | process 1 gate len =
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− | | process 1 gate len Δ =
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− | | process 1 cpp = 90 nm
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− | | process 1 cpp Δ = 0.77x
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− | | process 1 mmp = 64 nm
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− | | process 1 mmp Δ = 0.67x
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− | | process 1 sram hp =
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− | | process 1 sram hp Δ =
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− | | process 1 sram hd = 0.081 µm²
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− | | process 1 sram hd Δ = 0.64x
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− | | process 1 sram lv =
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− | | process 1 sram lv Δ =
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− | | process 1 dram =
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− | | process 1 dram Δ =
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− | <!-- IBM -->
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− | | process 2 fab = [[Common Platform Alliance]] <info>The '''Common Platform Alliance''' 20 nm node was a collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[Toshiba]], [[STMicroelectronics]]</info>
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− | | process 2 name =
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− | | process 2 date = 2014
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− | | process 2 lith = 193 nm
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− | | process 2 immersion = Yes
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− | | process 2 exposure =
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− | | process 2 wafer type = Bulk
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− | | process 2 wafer size = 300 mm
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− | | process 2 transistor = Planar
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− | | process 2 volt = 0.9 V
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− | | process 2 layers =
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− | | process 2 delta from = [[28 nm]] Δ
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− | | process 2 gate len = 20 nm
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− | | process 2 gate len Δ = 0.67x
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− | | process 2 cpp = 86 nm
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− | | process 2 cpp Δ = 0.76
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− | | process 2 mmp = 64 nm
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− | | process 2 mmp Δ = 0.71x
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− | | process 2 sram hp = 0.102 µm²
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− | | process 2 sram hp Δ =
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− | | process 2 sram hd = 0.081 µm²
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− | | process 2 sram hd Δ = 0.68x
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− | | process 2 sram lv =
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− | | process 2 sram lv Δ =
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− | | process 2 dram =
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− | | process 2 dram Δ =
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− | }} | |
− | | |
− | === TSMC ===
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− | TSMC demonstrated their 112 Mebibit [[SRAM]] wafer from their 20 nm HKMG process at the 2013 IEEE ISSCC.
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− | {| class="collapsible collapsed wikitable"
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− | |-
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− | ! colspan="2" | TSMC 112 Mib SRAM demo 20 nm wafer
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− | |-
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− | |
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− | <table class="wikitable">
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− | <tr><th>Technology</th><td>20 nm HK-MG</td></tr>
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− | <tr><th>Metal scheme</th><td>1 Poly / 7 Metal</td></tr>
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− | <tr><th>Supply voltage</th><td>0.95 V (core)<br>1.8 V (i/o)</td></tr>
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− | <tr><th>Bit cell size</th><td>0.081 µm²</td></tr>
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− | <tr><th>macro configs</th><td>2048x134 MUX4</td></tr>
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− | <tr><th>Capacity</th><td>112 Mib</td></tr>
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− | <tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
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− | <tr><th>Die Size</th><td>6400 µm x 6300 µm = 40.32 mm²</td></tr>
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− | </table>
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− | | [[File:tsmc 20nm SRAM block.png|400px]]
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− | |}
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− | == 20 nm Microprocessors== | + | == 20 nm System on Chips== |
− | * MediaTek
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− | ** {{mediatek|Helio}}
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− | * Fujitsu
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− | ** {{fujitsu|SPARC64}}
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− | * Oracle
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− | ** {{oracle|SPARC M8}}
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| {{expand list}} | | {{expand list}} |
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| == 20 nm Microarchitectures== | | == 20 nm Microarchitectures== |
| {{expand list}} | | {{expand list}} |
− | | + | [[Category:Lithography]] |
− | == References ==
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− | * Chang, Jonathan, et al. "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. IEEE, 2013.
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− | * Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
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− | [[category:lithography]] | |