Editing 16 nm lithography process

{{lithography processes}}
The '''16 nanometer (16 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[20 nm lithography process|20 nm process]] stopgap. Commercial [[integrated circuit]] manufacturing using 16 nm process began in 2014. The term "16 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. This technology is set to be replaced with [[10 nm lithography process|10 nm process]] in 2017.

== Industry ==
An enhanced version of TSMC's 16nm process was introduced in late 2016 called "12nm".
{{finfet nodes comp
<!-- Intel -->
 | process 1 fab          = [[TSMC]]
 | process 1 name         = 16FF<info>16nm FinFET</info>, 16FF+<info>16nm FinFET Plus</info>, 16FFC, 12FFC<info>12nm FinFET Compact</info>, 12FFN
 | process 1 date         = 3Q 2015
 | process 1 lith         = 193 nm
 | process 1 immersion    = Yes
 | process 1 exposure     = &nbsp;
 | process 1 wafer type   = Bulk
 | process 1 wafer size   = 300 mm
 | process 1 transistor   = FinFET
 | process 1 volt         = 0.75 V
 | process 1 delta from   = [[20 nm]] Δ
 | process 1 fin pitch    = 48 nm
 | process 1 fin pitch Δ  = -
 | process 1 fin width    = &nbsp;
 | process 1 fin width Δ  = 
 | process 1 fin height   = 37 nm
 | process 1 fin height Δ = 
 | process 1 gate len     = 34 nm
 | process 1 gate len Δ   = 
 | process 1 cpp          = 90 nm
 | process 1 cpp Δ        = 1x
 | process 1 mmp          = 64 nm
 | process 1 mmp Δ        = 1x
 | process 1 sram hp      = &nbsp;
 | process 1 sram hp Δ    = &nbsp;
 | process 1 sram hd      = 0.074 µm²
 | process 1 sram hd Δ    = 0.86x
 | process 1 sram lv      = &nbsp;
 | process 1 sram lv Δ    = &nbsp;
 | process 1 dram         = &nbsp;
 | process 1 dram Δ       = &nbsp;
}}

=== TSMC ===
[[File:tsmc 16nm.jpg|right|300px]]
TSMC uses the same [[BEOL]] as its 20nm process. They named their process 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly 10-15% performance improvement. A final 16FFC (16FF Compact) designed to reduce cost through less masks while using half the power. 

In late 2016 TSMC announced a "12nm" process (e.g. 12FFC<info>12nm FinFET Compact Technology</info>) which uses the same design rules as the 16nm node. The enhanced process is said to feature lower leakage better and cost characteristics and perhaps a better name (vs. "14nm"). 12nm is expected to enter mass production in late 2017.

{| class="collapsible collapsed wikitable"
|-
! colspan="2" | TSMC 128 Mib SRAM demo 16 nm wafer
|-
|
<table class="wikitable">
<tr><th>Technology</th><td>16 nm HK-MG FinFET</td></tr>
<tr><th>Metal scheme</th><td>1 Poly  / 7 Metal</td></tr>
<tr><th>Supply voltage</th><td>0.85 V (core)<br>1.8 V (i/o)</td></tr>
<tr><th>Bit cell size</th><td>0.07 µm²</td></tr>
<tr><th>macro configs</th><td>4096x32 MUX16<br>258 bits/BL<br>272 bits/WL</td></tr>
<tr><th>Capacity</th><td>128 Mib</td></tr>
<tr><th>Test Features</th><td>Row/Column Redundancy<br>Programmable E-fuse</td></tr>
<tr><th>Die Size</th><td>42.6 mm²</td></tr>
</table>
| [[File:tsmc 16nm SRAM block.png|400px]]
|}

== 16 nm Microprocessors==
* HiSilicon
** {{hisil|Kirin}}
* MediaTek
** {{mediatek|Helio}}
* Microsoft
** {{microsoft|Scorpio Engine}}
* Nvidia
** {{nvidia|Drive Xavier}}
** {{nvidia|Pascal}}
* PEZY
** {{pezy|PEZY-SC2}}
* Renesas
** {{renesas|R-Car}}
{{expand list}}

== 16 nm Microarchitectures==
* AppliedMicro/Ampere
** {{apm|Skylark|l=arch}}
* ARM
** {{armh|Cortex-A55|l=arch}}
* Phytium
** {{phytium|Mars II|l=arch}}
* Zhaoxin
** {{zhaoxin|LuJiaZui|l=arch}}
{{expand list}}

== References ==
* Chen, Yen-Huei, et al. "A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications." IEEE Journal of Solid-State Circuits 50.1 (2015): 170-177.
* Wu, Shien-Yang, et al. "A 16nm FinFET CMOS technology for mobile SoC and computing applications." Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE, 2013.
* TechInsights/Chipworks, Kevin Gibb, The ConFab 2016


[[category:lithography]]