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Editing 16 nm lithography process
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<!-- Intel --> | <!-- Intel --> | ||
| process 1 fab = [[TSMC]] | | process 1 fab = [[TSMC]] | ||
− | | process 1 name = 16FF | + | | process 1 name = 16FF, 16FF+, 12FFN |
− | | process 1 date = | + | | process 1 date = 2016 |
| process 1 lith = 193 nm | | process 1 lith = 193 nm | ||
| process 1 immersion = Yes | | process 1 immersion = Yes | ||
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=== TSMC === | === TSMC === | ||
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TSMC uses the same [[BEOL]] as its 20nm process. They named their process 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly 10-15% performance improvement. A final 16FFC (16FF Compact) designed to reduce cost through less masks while using half the power. | TSMC uses the same [[BEOL]] as its 20nm process. They named their process 16 nm which reflects those relaxed pitches. TSMC demonstrated their 128 Mebibit [[SRAM]] wafer from their 16 nm HKMG FinFET process at the 2014 IEEE ISSCC. TSMC followed their 16FF process by the 16FF+ which provided roughly 10-15% performance improvement. A final 16FFC (16FF Compact) designed to reduce cost through less masks while using half the power. | ||
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{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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== 16 nm Microprocessors== | == 16 nm Microprocessors== | ||
− | * | + | * PEZY |
− | ** {{ | + | ** {{pezy|PEZY-SC2}} |
* MediaTek | * MediaTek | ||
** {{mediatek|Helio}} | ** {{mediatek|Helio}} | ||
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* Renesas | * Renesas | ||
** {{renesas|R-Car}} | ** {{renesas|R-Car}} | ||
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== 16 nm Microarchitectures== | == 16 nm Microarchitectures== | ||
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* ARM | * ARM | ||
** {{armh|Cortex-A55|l=arch}} | ** {{armh|Cortex-A55|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
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− | [[ | + | [[Category:Lithography]] |