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{{lithography processes}} | {{lithography processes}} | ||
− | The '''10 nanometer (10 nm) lithography process''' is a | + | The '''10 nanometer (10 nm) lithography process''' is a semiconductor manufacturing [[process node]] serving as [[process shrink|shrink]] from the [[14 nm process]]. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. The 10 nm node is currently being introduced and is set to get replaced by the [[7 nm process]] in 2019. |
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== Industry == | == Industry == | ||
At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]]. | ||
− | Due to marketing names | + | Due to marketing names the transistor sizes vary considerably between leading manufactures. For example, Intel's 10nm process is denser and smaller than [[TSMC]]'s [[7 nm process]] while [[Samsung]]'s 10 nm process is more similar to Intel's [[14 nm process]] (e.g., a metal pitch just 1 nanometer shorter). |
{{10 nm comp | {{10 nm comp | ||
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| process 1 fab = [[Intel]] | | process 1 fab = [[Intel]] | ||
| process 1 name = P1274 (CPU) / P1275 (SoC) | | process 1 name = P1274 (CPU) / P1275 (SoC) | ||
− | | process 1 date = | + | | process 1 date = 2017 |
| process 1 lith = 193 nm | | process 1 lith = 193 nm | ||
| process 1 immersion = Yes | | process 1 immersion = Yes | ||
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| process 1 wafer size = 300 mm | | process 1 wafer size = 300 mm | ||
| process 1 transistor = FinFET | | process 1 transistor = FinFET | ||
− | | process 1 volt = | + | | process 1 volt = |
| process 1 delta from = [[14 nm]] Δ | | process 1 delta from = [[14 nm]] Δ | ||
| process 1 fin pitch = 34 nm | | process 1 fin pitch = 34 nm | ||
| process 1 fin pitch Δ = 0.81x | | process 1 fin pitch Δ = 0.81x | ||
− | | process 1 fin width = | + | | process 1 fin width = |
− | | process 1 fin width Δ = | + | | process 1 fin width Δ = |
| process 1 fin height = 53 nm | | process 1 fin height = 53 nm | ||
| process 1 fin height Δ = 1.26x | | process 1 fin height Δ = 1.26x | ||
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<!-- TSMC --> | <!-- TSMC --> | ||
| process 2 fab = [[TSMC]] | | process 2 fab = [[TSMC]] | ||
− | | process 2 name = | + | | process 2 name = |
− | | process 2 date = | + | | process 2 date = 2017 |
| process 2 lith = 193 nm | | process 2 lith = 193 nm | ||
| process 2 immersion = Yes | | process 2 immersion = Yes | ||
− | | process 2 exposure = | + | | process 2 exposure = |
| process 2 wafer type = Bulk | | process 2 wafer type = Bulk | ||
| process 2 wafer size = 300 mm | | process 2 wafer size = 300 mm | ||
| process 2 transistor = FinFET | | process 2 transistor = FinFET | ||
− | | process 2 volt = | + | | process 2 volt = |
| process 2 delta from = [[16 nm]] Δ | | process 2 delta from = [[16 nm]] Δ | ||
− | | process 2 fin pitch = | + | | process 2 fin pitch = |
− | | process 2 fin pitch Δ = | + | | process 2 fin pitch Δ = |
− | | process 2 fin width = | + | | process 2 fin width = |
| process 2 fin width Δ = | | process 2 fin width Δ = | ||
− | | process 2 fin height = | + | | process 2 fin height = |
− | | process 2 fin height Δ = | + | | process 2 fin height Δ = |
| process 2 gate len = | | process 2 gate len = | ||
| process 2 gate len Δ = | | process 2 gate len Δ = | ||
− | | process 2 cpp = | + | | process 2 cpp = 64 nm |
− | | process 2 cpp Δ = 0. | + | | process 2 cpp Δ = 0.71x |
− | | process 2 mmp = | + | | process 2 mmp = 42 nm |
− | | process 2 mmp Δ = 0. | + | | process 2 mmp Δ = 0.66x |
| process 2 sram hp = | | process 2 sram hp = | ||
| process 2 sram hp Δ = | | process 2 sram hp Δ = | ||
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<!-- Samsung --> | <!-- Samsung --> | ||
| process 3 fab = [[Samsung]] | | process 3 fab = [[Samsung]] | ||
− | | process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power | + | | process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power Performance</info>, 10LPU<info>3<sup>rd</sup> generation; 10 nm Low Power Ultimate</info> |
− | | process 3 date = | + | | process 3 date = 2017 |
| process 3 lith = 193 nm | | process 3 lith = 193 nm | ||
| process 3 immersion = Yes | | process 3 immersion = Yes | ||
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| process 3 wafer size = 300 mm | | process 3 wafer size = 300 mm | ||
| process 3 transistor = FinFET | | process 3 transistor = FinFET | ||
− | | process 3 volt = | + | | process 3 volt = |
| process 3 delta from = [[14 nm]] Δ | | process 3 delta from = [[14 nm]] Δ | ||
− | | process 3 fin pitch = | + | | process 3 fin pitch = |
− | | process 3 fin pitch Δ = | + | | process 3 fin pitch Δ = |
| process 3 fin width = | | process 3 fin width = | ||
| process 3 fin width Δ = | | process 3 fin width Δ = | ||
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| process 3 cpp = 68 nm | | process 3 cpp = 68 nm | ||
| process 3 cpp Δ = 0.87x | | process 3 cpp Δ = 0.87x | ||
− | | process 3 mmp = | + | | process 3 mmp = 51 nm |
− | | process 3 mmp Δ = 0. | + | | process 3 mmp Δ = 0.80x |
| process 3 sram hp = 0.049 µm² | | process 3 sram hp = 0.049 µm² | ||
| process 3 sram hp Δ = 0.61x | | process 3 sram hp Δ = 0.61x | ||
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| process 4 wafer size = 300 mm | | process 4 wafer size = 300 mm | ||
| process 4 transistor = FinFET | | process 4 transistor = FinFET | ||
− | | process 4 volt = | + | | process 4 volt = |
| process 4 delta from = [[14 nm]] Δ | | process 4 delta from = [[14 nm]] Δ | ||
| process 4 fin pitch = | | process 4 fin pitch = | ||
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| process 4 fin height Δ = | | process 4 fin height Δ = | ||
| process 4 gate len = 20 nm | | process 4 gate len = 20 nm | ||
− | | process 4 gate len Δ = | + | | process 4 gate len Δ = |
| process 4 cpp = 64 nm | | process 4 cpp = 64 nm | ||
| process 4 cpp Δ = 0.80x | | process 4 cpp Δ = 0.80x | ||
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| process 4 dram Δ = | | process 4 dram Δ = | ||
}} | }} | ||
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=== Intel === | === Intel === | ||
{{see also|intel/process|l1=Intel's Process Technology History}} | {{see also|intel/process|l1=Intel's Process Technology History}} | ||
− | + | Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is the first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) with production starting in the second half of 2017. Intel detailed {{intel|Hyper-Scaling}}, a marketing term for a suite of techniques used to [[transistor scaling|scale a transistor]], SAQP, a single dummy gate and [[contact over active gate]] (COAG). | |
− | Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is | ||
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=== Samsung === | === Samsung === | ||
− | + | Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 mm contacted gate pitch, 51 nm metal pitch, dual-depth [[shallow trench isolation]] (STI), and had single dummy gate. | |
− | Samsung demonstrated their 128 | ||
{| class="collapsible collapsed wikitable" | {| class="collapsible collapsed wikitable" | ||
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| [[File:samsung 10nm SRAM block.png|400px]] | | [[File:samsung 10nm SRAM block.png|400px]] | ||
|} | |} | ||
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== 10 nm Microprocessors== | == 10 nm Microprocessors== | ||
− | + | * MediaTek | |
− | {{ | + | ** {{mediatek|Helio}} |
− | + | * Qualcomm | |
− | + | ** {{qualcomm|Snapdragon 800}} | |
− | + | ** {{qualcomm|Centriq}} | |
− | + | * Xiaomi | |
− | + | ** {{xiaomi|Surge}} | |
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− | }} | ||
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{{expand list}} | {{expand list}} | ||
== 10 nm Microarchitectures== | == 10 nm Microarchitectures== | ||
* Intel | * Intel | ||
− | + | ** {{intel|Cannonlake|l=arch}} | |
− | + | ** {{intel|Icelake|l=arch}} | |
− | + | ** {{intel|Tigerlake|l=arch}} | |
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* Qualcomm | * Qualcomm | ||
** {{qualcomm|Falkor|l=arch}} | ** {{qualcomm|Falkor|l=arch}} | ||
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{{expand list}} | {{expand list}} | ||
== Documents == | == Documents == | ||
* [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] | * [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] | ||
− | * [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel | + | * [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm]] |
− | * [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel | + | * [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel Technoogy & Manufacturing Day presentation, 10 nm / Moore's Law]] |
== References == | == References == | ||
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* Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | * Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | ||
* Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | * Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | ||
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− | [[ | + | [[Category:Lithography]] |