| Latest revision |
Your text |
| Line 1: |
Line 1: |
| | {{lithography processes}} | | {{lithography processes}} |
| − | The '''10 nanometer (10 nm) lithography process''' is a [[semiconductor manufacturing]] [[process node]] serving as [[process shrink|shrink]] from the [[14 nm process]]. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to [[gate length]] or [[half pitch]]. The 10 nm node is currently being introduced and is set to get replaced by the [[7 nm process]] in 2018/2019. | + | The '''10 nanometer (10 nm) lithography process''' is a [[technology node|full node]] semiconductor manufacturing process following the [[14 nm lithography process|14 nm process]] stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of [[integrated circuit]] manufacturing using 10 nm process begun in late 2016. This technology is set to be replaced by [[7 nm lithography process|7 nm process]] 2019. |
| − | | |
| − | == Overview ==
| |
| − | First introduced between 2017-2019, the 10 nm [[process technology]] is characterized by its use of [[FinFET]] transistors with a 30-40s nm [[fin pitches]]. Those nodes typically have a [[gate pitch]] in range of 50-60s nm and a [[minimum metal pitch]] in the range of 30-40s nm. Due to the small feature sizes, for the [[critical dimensions]], [[quad patterning|quad]] and [[triple patterning|triple]] [[multiple patterning|patterning]] were introduced for the first time in [[high-volume manufacturing]].
| |
| − | | |
| | == Industry == | | == Industry == |
| − | At the advanced 10nm process, there are only 3 semiconductor foundries with such manufacturing capabilities: [[Intel]], [[Samsung]], and [[TSMC]].
| + | {{future information}} |
| − | | |
| − | Due to marketing names, geometries vary greatly between leading manufacturers. Although both TSMC and Samsung's 10nm processes are slightly denser than Intel's 14nm in raw logic density, they are far closer to Intel's 14nm than they are to Intel's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm).
| |
| | | | |
| − | {{10 nm comp
| |
| − | <!-- Intel -->
| |
| − | | process 1 fab = [[Intel]]
| |
| − | | process 1 name = P1274 (CPU) / P1275 (SoC)
| |
| − | | process 1 date = 2018
| |
| − | | process 1 lith = 193 nm
| |
| − | | process 1 immersion = Yes
| |
| − | | process 1 exposure = [[Self-Aligned Quad Patterning|SAQP]]
| |
| − | | process 1 wafer type = Bulk
| |
| − | | process 1 wafer size = 300 mm
| |
| − | | process 1 transistor = FinFET
| |
| − | | process 1 volt = 0.70 V
| |
| − | | process 1 delta from = [[14 nm]] Δ
| |
| − | | process 1 fin pitch = 34 nm
| |
| − | | process 1 fin pitch Δ = 0.81x
| |
| − | | process 1 fin width = 7 nm
| |
| − | | process 1 fin width Δ = 0.88x
| |
| − | | process 1 fin height = 53 nm
| |
| − | | process 1 fin height Δ = 1.26x
| |
| − | | process 1 gate len =
| |
| − | | process 1 gate len Δ =
| |
| − | | process 1 cpp = 54 nm
| |
| − | | process 1 cpp Δ = 0.77x
| |
| − | | process 1 mmp = 36 nm
| |
| − | | process 1 mmp Δ = 0.69x
| |
| − | | process 1 sram hp = 0.0441 µm²
| |
| − | | process 1 sram hp Δ = 0.62x
| |
| − | | process 1 sram hd = 0.0312 µm²
| |
| − | | process 1 sram hd Δ = 0.62x
| |
| − | | process 1 sram lv = 0.0367 µm²
| |
| − | | process 1 sram lv Δ = 0.62x
| |
| − | | process 1 dram =
| |
| − | | process 1 dram Δ =
| |
| | | | |
| − | <!-- TSMC -->
| + | {{scrolling table/top|style=text-align: right; | first=Fab |
| − | | process 2 fab = [[TSMC]]
| + | |Process Name |
| − | | process 2 name = 10FF
| + | |1st Production |
| − | | process 2 date = June 2017
| + | |Transistor |
| − | | process 2 lith = 193 nm
| + | | |
| − | | process 2 immersion = Yes
| + | |Fin Pitch |
| − | | process 2 exposure = SAQP
| + | |Fin Width |
| − | | process 2 wafer type = Bulk
| + | |Fin Height |
| − | | process 2 wafer size = 300 mm
| + | |Contacted Gate Pitch |
| − | | process 2 transistor = FinFET
| + | |Interconnect Pitch (M1P) |
| − | | process 2 volt = 0.70 V
| + | |SRAM bit cell (HP) |
| − | | process 2 delta from = [[16 nm]] Δ
| + | |SRAM bit cell (HD) |
| − | | process 2 fin pitch = 36 nm | |
| − | | process 2 fin pitch Δ = 0.75x | |
| − | | process 2 fin width = 6 nm | |
| − | | process 2 fin width Δ = | |
| − | | process 2 fin height = 42 nm | |
| − | | process 2 fin height Δ = 1.35x | |
| − | | process 2 gate len = | |
| − | | process 2 gate len Δ = | |
| − | | process 2 cpp = 66 nm <sub>(64 nm<sup>*</sup>)</sub> | |
| − | | process 2 cpp Δ = 0.73x | |
| − | | process 2 mmp = 44 nm <sub>(42 nm<sup>*</sup>)</sub> | |
| − | | process 2 mmp Δ = 0.69x
| |
| − | | process 2 sram hp =
| |
| − | | process 2 sram hp Δ =
| |
| − | | process 2 sram hd = 0.042 µm²
| |
| − | | process 2 sram hd Δ = 0.57x
| |
| − | | process 2 sram lv =
| |
| − | | process 2 sram lv Δ =
| |
| − | | process 2 dram =
| |
| − | | process 2 dram Δ =
| |
| − | | |
| − | <!-- Samsung -->
| |
| − | | process 3 fab = [[Samsung]]
| |
| − | | process 3 name = 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power Plus</info>, 10LPU<info>3<sup>rd</sup> generation; 10 nm Low Power Ultimate</info>
| |
| − | | process 3 date = April 2017
| |
| − | | process 3 lith = 193 nm
| |
| − | | process 3 immersion = Yes
| |
| − | | process 3 exposure = [[LELELE]]
| |
| − | | process 3 wafer type = Bulk
| |
| − | | process 3 wafer size = 300 mm
| |
| − | | process 3 transistor = FinFET
| |
| − | | process 3 volt = 0.75 V
| |
| − | | process 3 delta from = [[14 nm]] Δ
| |
| − | | process 3 fin pitch = 42 nm
| |
| − | | process 3 fin pitch Δ = 0.88x
| |
| − | | process 3 fin width =
| |
| − | | process 3 fin width Δ =
| |
| − | | process 3 fin height =
| |
| − | | process 3 fin height Δ =
| |
| − | | process 3 gate len =
| |
| − | | process 3 gate len Δ =
| |
| − | | process 3 cpp = 68 nm
| |
| − | | process 3 cpp Δ = 0.87x
| |
| − | | process 3 mmp = 48 nm
| |
| − | | process 3 mmp Δ = 0.75x
| |
| − | | process 3 sram hp = 0.049 µm²
| |
| − | | process 3 sram hp Δ = 0.61x
| |
| − | | process 3 sram hd = 0.040 µm²
| |
| − | | process 3 sram hd Δ = 0.63x
| |
| − | | process 3 sram lv =
| |
| − | | process 3 sram lv Δ =
| |
| − | | process 3 dram =
| |
| − | | process 3 dram Δ =
| |
| − | | |
| − | <!-- Common Platform -->
| |
| − | | |
| − | | process 4 fab = [[Common Platform Alliance]]<info>The '''Common Platform Alliance''' is a joint collaboration between [[IBM]], [[Samsung]], [[GlobalFoundries]], [[STMicroelectronics]], [[UMC]]</info> Paper
| |
| − | | process 4 name =
| |
| − | | process 4 date =
| |
| − | | process 4 lith = 193 nm
| |
| − | | process 4 immersion = Yes
| |
| − | | process 4 exposure = SADP
| |
| − | | process 4 wafer type = Bulk/SOI
| |
| − | | process 4 wafer size = 300 mm
| |
| − | | process 4 transistor = FinFET
| |
| − | | process 4 volt = 0.75 V
| |
| − | | process 4 delta from = [[14 nm]] Δ
| |
| − | | process 4 fin pitch =
| |
| − | | process 4 fin pitch Δ =
| |
| − | | process 4 fin width =
| |
| − | | process 4 fin width Δ =
| |
| − | | process 4 fin height =
| |
| − | | process 4 fin height Δ =
| |
| − | | process 4 gate len = 20 nm
| |
| − | | process 4 gate len Δ = 1.00x;
| |
| − | | process 4 cpp = 64 nm
| |
| − | | process 4 cpp Δ = 0.80x
| |
| − | | process 4 mmp = 48 nm
| |
| − | | process 4 mmp Δ = 0.75x
| |
| − | | process 4 sram hp =
| |
| − | | process 4 sram hp Δ =
| |
| − | | process 4 sram hd = 0.053 µm²
| |
| − | | process 4 sram hd Δ = 0.65x
| |
| − | | process 4 sram lv =
| |
| − | | process 4 sram lv Δ =
| |
| − | | process 4 dram =
| |
| − | | process 4 dram Δ =
| |
| | }} | | }} |
| − | | + | {{scrolling table/mid}} |
| − | '''<sup>*</sup>''' - Value reported from IEEE ISSCC/IEDM/VLSI Conference.
| + | |- |
| − | | + | ! colspan="2" | [[Intel]] !! colspan="2" | [[Samsung]] !! colspan="2" | [[TSMC]] !! colspan="2" | [[SK Hynix]] |
| − | === Intel ===
| + | |- style="text-align: center;" |
| − | {{see also|intel/process|l1=Intel's Process Technology History}} | + | | colspan="2" | P1274 || colspan="2" | 10LPE<info>1<sup>st</sup> generation; 10 nm Low Power Early</info>, 10LPP<info>2<sup>nd</sup> generation; 10 nm Low Power Performance</info>, 10LPU<info>3<sup>rd</sup> generation; 10 nm Low Power Ultimate</info>|| colspan="2" | || colspan="2" | |
| − | [[File:intel 10nm fin.png|right|200px]] | + | |- style="text-align: center;" |
| − | Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is Intel's first high-volume manufacturing process to employ [[Self-Aligned Quad Patterning]] (SAQP) with production starting in the second half of 2017. Intel detailed {{intel|Hyper-Scaling}}, a marketing term for a suite of techniques used to [[transistor scaling|scale a transistor]], SAQP, a single dummy gate and [[contact over active gate]] (COAG). Intel's initial 10 nm process has up to 60% lower power and 25% better performance than their initial 14 nm but will actually have lower performance than their "14nm++" process. Intel expect their "10nm+" process to surpass that.
| + | | colspan="2" | 2017 || colspan="2" | 2017 || colspan="2" | 2017 || colspan="2" | 2017 |
| − | | + | |- style="text-align: center;" |
| − | Intel's 10nm process is roughly 1.7x the raw logic density of the next densest 10nm process, albeit due to aggressive pattering techniques they also have the most complex process available to date. The process can support multiple threshold voltages, and features 12-metal interconnect layers with the bottom two made of cobalt. This is the first time cobalt is used in a high volume production node. Because of the ever shrinking geometries the wires get smaller each node.
| + | | colspan="8" | FinFET |
| − | [[File:intel interconnect 10 nm.jpg|left|200px]]
| + | |- |
| − | At 10nm the wires become so small that the barrier layer takes up most of the interconnect, resulting in less space for the copper itself. As the cross section of the wire gets smaller the resistance rises exponentially. Cobalt aims to address this issue, it does not diffuse in the surrounding material, so the barrier layer can be reduced. And even though it has a higher resistance than copper in bulk, it has up to two times lower resistance in very small wires. This can be attributed to the larger wires because of the reduced barrier layer and the larger grain size, which reduces the electron scattering. It also has 10x better resistance to electron-migration.
| + | ! Value !! [[14 nm]] Δ !! Value !! [[14 nm]] Δ !! Value !! [[16 nm]] Δ !! Value !! [[18 nm]] Δ |
| − | | + | |- |
| − | Intel will leverage their initial 10nm process for their {{intel|Cannon Lake|l=arch}}-based microprocessors which are used exclusively for mobile. They will then utilize their second generation, "10nm+" process, for {{intel|Ice Lake|l=arch}}-based processors which will be used for the mainstream and server platform.
| + | | 34 nm || 0.81x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
| − | | + | |- |
| − | ===== Intel 7 Ultra ===== | + | | ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
| − | [[File:raptor-lake-v-f-curve-improvements.png|thumb|right|New V-F Curve for the Enhanced Intel 7 process.]] | + | |- |
| − | Intel introduced an '''enhanced version of the Intel 7 process''' in late 2022 with the introduction of the company's 13th Generation Core processors based on the {{intel|Raptor Lake|l=arch}} microarchitecture. Nicknamed '''"Intel 7 Ultra"''' internally, the new process is a full PDK update over the one used by Alder Lake, their 3rd generation SuperFin Transistor architecture. Intel says this process brings transistors with significantly better channel mobility. At the very high end of the V-F curve, the company says peak frequency is nearly 1 GHz higher now. The curve itself has been improved, shifting prior-generation frequencies by around 200 MHz at ISO-voltage, or alternatively, reducing the voltage by over 50 mV at ISO-frequency.
| + | | ? nm || ?x || ? nm || ?x || ? nm || ?x || ? nm || ?x |
| − | | + | |- |
| − | * [https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/ In-depth analysis for Intel's 10nm process.]
| + | | 54 nm || 0.77x || 64 nm || 0.82x || 64 nm || 0.71x || ? nm || ?x |
| − | | + | |- |
| − | {{clear}} | + | | 36 nm || 0.69x || 48 nm || 0.75x || 42 nm || 0.66x || ? nm || ?x |
| | + | |- |
| | + | | ? µm² || ?x || 0.049 µm² || 0.61x || ? µm² || ?x || ? nm || ?x |
| | + | |- |
| | + | | ? µm² || ?x || 0.040 µm² || 0.63x || ? µm² || ?x || ? nm || ?x |
| | + | {{scrolling table/end}} |
| | | | |
| | === Samsung === | | === Samsung === |
| − | [[File:ss 14-10nm.png|right|500px]]
| + | Samsung demonstrated their 128 Mebibit [[SRAM]] wafer from their 10nm FinFET process. |
| − | Samsung demonstrated their 128 Megabit [[SRAM]] wafer from their 10nm FinFET process. Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), ramped up mass production in May of 2017. ChipWorks/TechInsight measured the CPP/MMP which came a little short of the Common Platform Alliance Paper which was presented in 2016, at 68 nm contacted gate pitch, 51 nm metal pitch, dual-depth [[shallow trench isolation]] (STI), and had single dummy gate. | |
| | | | |
| | {| class="collapsible collapsed wikitable" | | {| class="collapsible collapsed wikitable" |
| Line 180: |
Line 58: |
| | <tr><th>Bit cell size</th><td>0.040 µm²</td></tr> | | <tr><th>Bit cell size</th><td>0.040 µm²</td></tr> |
| | <tr><th>macro configs</th><td>256x512 Kib</td></tr> | | <tr><th>macro configs</th><td>256x512 Kib</td></tr> |
| − | <tr><th>Capacity</th><td>128 Mib</td></tr> | + | <tr><th>Capacity</th><td>256 Mib</td></tr> |
| | <tr><th>Test Features</th><td>Programmable E-fuse</td></tr> | | <tr><th>Test Features</th><td>Programmable E-fuse</td></tr> |
| − | <tr><th>Die Size</th><td>75.6mm²</td></tr> | + | <tr><th>Die Size</th><td>75.6mm2²</td></tr> |
| | </table> | | </table> |
| | | [[File:samsung 10nm SRAM block.png|400px]] | | | [[File:samsung 10nm SRAM block.png|400px]] |
| | |} | | |} |
| − |
| |
| − | Samsung's initial process was 10LPE (10 Low-Power Early) which was replaced by second generation evolved process 10LPP (10 Low-Power Plus). Samsung intends to introduce a third generational enhanced 10nm process called 8LPP (8 Low Power Plus) which will further improve performance and introduce a small density increase through cell enhancements and a narrower metal pitch. 8LPP improvements over 10LPP is similar to their 11LPP improvements over their 14LPP. It's worth noting that Samsung intends 8LPP to be their last non-[[EUV]] node. All subsequent nodes will use EUV.
| |
| − |
| |
| − | === TSMC ===
| |
| − | TSMC reported a poly pitch of 64 nm with a metal pitch 42 nm. TechInsight measured them at 66 nm and 44 nm respectively. 10FF is the second process to use FinFET, and is the Industry's first use of Quad-Patterning. This allows for a full node shrink, enabling a 2X increase in logic density compared to their 16nm process. The 10FF process will have 15% higher performance while consuming 35% less power.
| |
| − | {{clear}}
| |
| − | [[File:10nm tsmc.jpeg|200px]]
| |
| | | | |
| | == 10 nm Microprocessors== | | == 10 nm Microprocessors== |
| − | | + | * MediaTek |
| − | {{#ask: [[Category:microprocessor families]] [[process::10 nm]] | + | ** {{mediatek|Helio}} |
| − | <!-- There are currently multiple designers per family, there should be a "main designer"
| + | * Qualcomm |
| − | |?main designer
| + | ** {{qualcomm|Snapdragon 800}} |
| − | -->
| + | ** {{qualcomm|Centriq}} |
| − | |format=ul
| + | * Xiaomi |
| − | |offset=0
| + | ** {{xiaomi|Surge}} |
| − | |link=all
| |
| − | |headers=show
| |
| − | |mainlabel=
| |
| − | |searchlabel=something like this
| |
| − | |columns=3
| |
| − | }} | |
| − | | |
| | {{expand list}} | | {{expand list}} |
| | | | |
| | == 10 nm Microarchitectures== | | == 10 nm Microarchitectures== |
| | * Intel | | * Intel |
| − | ** CPU
| + | ** {{intel|Cannonlake|l=arch}} |
| − | *** {{intel|Cannon Lake|l=arch}}
| + | ** {{intel|Icelake|l=arch}} |
| − | *** {{intel|Ice Lake (client)|l=arch}}
| + | ** {{intel|Tigerlake|l=arch}} |
| − | *** {{intel|Tiger Lake|l=arch}}
| |
| − | *** {{intel|Alder Lake|l=arch}}
| |
| − | *** {{intel|Ice Lake (server)|l=arch}}
| |
| − | *** {{intel|Sapphire Rapids|l=arch}}
| |
| − | *** {{intel|Tremont|l=arch}}
| |
| − | *** <s>{{intel|Knights Hill|l=arch}}</s>
| |
| − | ** GPU
| |
| − | *** {{intel|Arctic Sound|l=arch}}
| |
| − | *** {{intel|Jupiter Sound|l=arch}}
| |
| | * Qualcomm | | * Qualcomm |
| | ** {{qualcomm|Falkor|l=arch}} | | ** {{qualcomm|Falkor|l=arch}} |
| − | * Samsung
| |
| − | ** {{samsung|Mongoose 2|l=arch}}
| |
| − | ** {{samsung|Mongoose 3|l=arch}}
| |
| | {{expand list}} | | {{expand list}} |
| | | | |
| | == Documents == | | == Documents == |
| | * [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] | | * [[:File:10-nm-technology-fact-sheet.pdf|Intel's 10 nm Technology: Delivering the Highest Logic Transistor Density in the Industry Through the Use of Hyper Scaling]] |
| − | * [[:File:Kaizad-Mistry-2017-Manufacturing.pdf|Intel Technology & Manufacturing Day presentation, 10 nm]]
| |
| − | * [[:File:Mark-Bohr-2017-Moores-Law.pdf|Intel Technology & Manufacturing Day presentation, 10 nm / Moore's Law]]
| |
| | | | |
| | == References == | | == References == |
| − | * Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
| |
| − | * Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
| |
| − | * Seo, K-I., et al. "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
| |
| | * Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016. | | * Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016. |
| | * Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). | | * Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016). |
| − | * Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017. | + | * Intel data Based on a presentation by Mark Bohr, Intel |
| − | * Samsung's actual transistor size was measured by ChipWorks/TechInsight based on the [[Qualcomm]] {{qualcomm|Snapdragon 835}} which is manufactured on Samsung's 10nm process.
| |
| − | * [http://www.techinsights.com/technology-intelligence/overview/latest-reports/tsmc-10-nm-process/ TechInsights TSMC 10 nm Process Analysis]
| |
| | | | |
| − | [[category:lithography]] | + | [[Category:Lithography]] |
