Page title matches

• mirc/optimization
  {{mirc title|Optimization}} [[Category:mIRC|optimization]]
  13 KB (2,047 words) - 06:44, 23 February 2023
• intel/process-architecture-optimization
  {{intel title|Process-Architecture-Optimization (PAO)}} '''[[name::Process-Architecture-Optimization]]''' was a temporary [[instance of::development model]] introduced by [[Int
  3 KB (357 words) - 20:33, 8 November 2019

Page text matches

• mosfet
  ...ast2=Sylvester |first3=David|last3=Blaauw | title=Statistical Analysis and Optimization For VLSI: Timing and Power | year = 2005 | page=135 | publisher=Springer | ...last=Barke | title = Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop) | year = 2000 | page = [https://archiv
  193 KB (26,874 words) - 17:01, 6 September 2024
• intel
  * {{\\|Process-Architecture-Optimization}} (PAO)
  9 KB (1,153 words) - 04:45, 6 November 2024
• mirc/sendmessage
  If you feel there are areas of your site that could benefit from optimization, I provide tailored SEO services to help drive more traffic and enhance its
  642 bytes (108 words) - 03:26, 21 November 2024
• schlemiel the painter's algorithm
  [[category:optimization]]
  4 KB (646 words) - 23:56, 20 February 2016
• compound logic gate
  ...designers (simply due to their complexity), those gates are often used by optimization programs are able to make efficient use of such gates.
  1 KB (178 words) - 14:46, 23 November 2015
• boolean algebra/majority function
  ...t{MAJ}(a, b, c)}</math> which could yields various hardware implementation optimization - such as floating the [[inversion bubble|inversion point]] to a more desir
  2 KB (368 words) - 20:04, 15 December 2015
• mirc/optimization
  {{mirc title|Optimization}} [[Category:mIRC|optimization]]
  13 KB (2,047 words) - 06:44, 23 February 2023
• mirc/optization
  #REDIRECT [[mirc/optimization]]
  31 bytes (3 words) - 19:22, 15 December 2015
• amd/athlon
  ...on Processor x86 Code Optimization Guide.pdf|AMD Athlon Processor x86 Code Optimization Guide]]; Publication No. 22007; Revision K; Date February 2002. ...on Processor x86 Code Optimization Guide.pdf|AMD Athlon Processor x86 Code Optimization Guide]] have serious bugs and return wrong results<ref>[https://community.a
  10 KB (1,163 words) - 09:41, 26 February 2019
• 14 nm lithography process
  ...% increase in density and 10% increase in performance through further cell optimization such as [[track reduction]].
  17 KB (2,243 words) - 18:32, 25 May 2023
• intel/microarchitectures/bonnell
  ...delay. The inability to execute things [[out-of-order]] eliminates lots of optimization opportunities at this stage. One thing Bonnell can do is lockstep instructi * Corporation, Intel. "Intel 64 and IA-32 architectures optimization reference manual." (2009).
  38 KB (5,468 words) - 19:29, 23 May 2019
• intel/microarchitectures/sandy bridge (client)
  One key optimization the instruction queue does is [[macro-op fusion]]. Sandy Bridge can fuse tw ...ptimizations are [[Zeroing Idioms]], and [[Ones Idioms]]. The first common optimization performed in Sandy Bridge is [[Zeroing Idioms]] elimination or a dependency
  84 KB (13,075 words) - 23:54, 28 December 2020
• intel/microarchitectures/p6
  * [[:File:24281603.pdf|Intel Architecture Optimization Manual]], Document 242816-003; 1997
  3 KB (325 words) - 20:34, 22 February 2020
• intel/microarchitectures/skylake (client)
  ...50 total entries). It's unclear if that has changed with Skylake. One key optimization the instruction queue does is [[macro-op fusion]]. Skylake can fuse two [[m ...ucceed; when it fails, the operands were simply not ready. On average this optimization is almost always successful (upward of 85% in most cases). Move elimination
  79 KB (11,922 words) - 01:42, 16 November 2024
• intel/microarchitectures/kaby lake
  ...ture]] for mainstream desktops and mobile devices. Kaby Lake is the first "Optimization" released as part of Intel's {{intel|PAO}} model. The microarchitecture was
  38 KB (5,431 words) - 09:41, 8 April 2024
• 10 nm lithography process
  ...128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
  14 KB (1,903 words) - 05:52, 17 February 2023
• x86/umip
  * Software Optimization Guide for AMD Family 17h Models 30h and Greater Processors
  2 KB (338 words) - 00:25, 30 December 2019
• 2016
  ...their {{intel|Tick-Tock}} model in favor of a {{intel|Process-Architecture-Optimization}} model.
  5 KB (593 words) - 00:28, 5 August 2018
• intel/tick-tock
  ...longer uses this model, instead they use the {{intel|Process-Architecture-Optimization}} (PAO).
  3 KB (317 words) - 21:13, 30 April 2017
• intel/process-architecture-optimization
  {{intel title|Process-Architecture-Optimization (PAO)}} '''[[name::Process-Architecture-Optimization]]''' was a temporary [[instance of::development model]] introduced by [[Int
  3 KB (357 words) - 20:33, 8 November 2019

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