x86
Instruction Set Architecture

General

• History
• Families

Variants

• x86-16
• x86-32
• x86-64

Topics

• Instructions
• Addressing Modes
• Registers
• Model-Specific Register
• Assembly
• Interrupts
• Micro-Ops
• Timer
• Calling Convention
• Microarchitectures
• CPUID

CPUIDs

• AMD's CPUIDs
• Intel's CPUIDs

Modes

• Real
• Protected
• Long

Extensions(all)

• 3DNow!
• ABM
• ADX
• AES
• AMX
• AVX
• AVX2
• AVX-512
• BMI1
• BMI2
• CLMUL
• E3DNow!
• EMMX
• F16C
• FMA3
• FMA4
• FPU
• MKTME
• MMX
• MPX
• PMEM
• PREFETCH
• RdRAND
• SEV
• SGX
• SHA
• SME
• SMM
• SMX
• SSE
• SSE2
• SSE3
• SSE4.1
• SSE4.2
• SSE4a
• SSE5
• SSSE3
• TBM
• TME
• TSME
• TSX
• XOP

ADX is an x86 instruction set extension that introduced arbitrary-precision arithmetic operations.

Overview

ADX introduced two new instructions:

• ADCX
• ADOX

They are similar to the ADC instruction by doing a add with overflow, but

• ADCX uses the Carry flag as source and destination of overflow and leaves the other flags untouched
• ADOX uses the Overflow flag as source and destination of overflow and leaves the other flags untouched

This allows two parallel addition of multi-precision numbers because both have their separate carry flag.

Note:

• To add a constant to a register without affecting flags, you can use the LEA reg, [reg + n] instruction

    xor  rax, rax
 lbl:
    mov  rbx, [r8 + r15]
    adcx rbx, [r9 + r15]
    mov  [r9 + r15], rbx
    mov  rbx, [r10 + r15]
    adox rbx, [r11 + r15]
    mov  [r11 + r15], rbx
    lea  r15, [r15 + 8]
    dec  r14
    jnz  lbl