Semiconductor & Computer Engineering
From WikiChip
SC2A11 - Socionext
| Edit Values | |
| Socionext SC2A11 | |
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| General Info | |
| Designer | Socionext, ARM Holdings |
| Model Number | SC2A11 |
| Market | Server, Networking, IoT |
| Introduction | November 14, 2016 (announced) 2017 (launched) |
| General Specs | |
| Frequency | 1,000 MHz |
| Bus type | AMBA |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A53 |
| Core Name | Cortex-A53 |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 24 |
| Threads | 24 |
| Max Memory | 64 GiB |
| Multiprocessing | |
| Max SMP | 64-Way (Multiprocessor) |
| Electrical | |
| TDP | 5 W |
SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to 64 GiB of DDR4-2133 ECC memory.
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
This SoC has no integrated graphics processing unit.
Networking
- 2x Gigabit Ethernet Interfaces
Storage
- SPI
- eMMC
Block diagram
Facts about "SC2A11 - Socionext"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | SC2A11 - Socionext#io + |
| base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
| bus type | AMBA + |
| core count | 24 + |
| core name | Cortex-A53 + |
| designer | Socionext + and ARM Holdings + |
| first announced | November 14, 2016 + |
| first launched | 2017 + |
| full page name | socionext/sc2a11 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| ldate | 3000 + |
| main image |  + |
| market segment | Server +, Networking + and IoT + |
| max cpu count | 64 + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 4 + |
| microarchitecture | Cortex-A53 + |
| model number | SC2A11 + |
| name | Socionext SC2A11 + |
| smp max ways | 64 + |
| supported memory type | DDR4-2133 + |
| tdp | 5 W (5,000 mW, 0.00671 hp, 0.005 kW) + |
| technology | CMOS + |
| thread count | 24 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
