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Godson-2H
Godson-2H chip
General Info
Designer	Loongson
Manufacturer	STMicroelectronics
Model Number	2H
Market	Desktop
Introduction	August, 2010 (announced) March, 2011 (launched)
General Specs
Family	Godson 2
Series	Godson 2
Frequency	1,000 MHz
Bus type	HyperTransport 1.03
Bus speed	800 MHz
Microarchitecture
ISA	MIPS64 (MIPS)
Microarchitecture	GS464V
Core Name	GS464V
Process	65 nm
Transistors	152,000,000
Technology	CMOS
Die	117 mm²
Word Size	64 bit
Cores	1
Threads	1
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Power dissipation	10 W

Godson-2H (龙芯2H) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2H operates at up to 1 GHz consuming up to 10 W. This chip was manufactured on STMicroelectronics' 65 nm process.

The Godson-2H is actually a complete system on a chip incorporating the northbridge along with the southbridge on-die. Additionally the Godson-2H also incorporates a low-power Vivante GC800 IGP operating at 400 MHz.

In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative southbridge to the more powerful Godson 3 multi-core processor family.

Cache

Main article: GS464V § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 4-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Max Mem 4 GiB Controllers 1 Channels 1 Max Bandwidth 11.92 GiB/s 12,206.08 MiB/s 12.799 GB/s 12,799.003 MB/s 0.0116 TiB/s 0.0128 TB/s Bandwidth Single 11.92 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU GC800 Designer Vivante Execution Units 4 Frequency 400 MHz 0.4 GHz 400,000 KHz Output VGA, SDVO, CRT Max Resolution DSI 1920x1080 VGA 1920x1080 Standards DirectX 11 OpenGL 3.0 OpenCL 1.1 OpenGL ES 2.0

Expansions

This chip has integrated HyperTransport 1.03 operating at 200, 400, or 800 MHz.

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 2.0 Max Lanes 4 Configs 1x4, 4x1 USB Revision 2.0 Ports 6 SATA Revision 2 Ports 2 LPC Revision 1.1 I²C Ports 2 GP I/O 16 lines JTAG Yes

Networking

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes SPI

Die Shot

• 65 nm process
• 152,000,000 transistors
• 117 mm² die size

References

• Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.
• Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")