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CN8020 - Cavium
Edit Values | |
Octeon TX CN8020 | |
General Info | |
Designer | Cavium |
Market | Storage |
General Specs | |
Family | OCTEON TX |
Series | CN80xx |
Frequency | 1,500MHz |
Microarchitecture | |
ISA | ArmV8 (ARM) |
Microarchitecture | Armv8.1 |
Technology | CMOS |
Word Size | 64 bit |
Cores | 2 |
Threads | 2 |
Max Memory | 16GB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
CN8020 is a 64-bit dual-core ARM processor designed by Cavium. This processor, which incorporates 2 thunderx1 cores. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as networking, TCP & QoS, and crypto acceleration.
Contents
Cache
- Main articles: cavium/microarchitectures/thunderx1 and Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Interface options:
Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN8020 - Cavium"
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
core count | 2 + |
designer | Cavium + |
family | OCTEON TX + |
full page name | cavium/octeon tx/cn8020 + |
has ecc memory support | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | ArmV8 + |
isa family | ARM + |
l1$ size | 208 KiB (212,992 B, 0.203 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 144 KiB (147,456 B, 0.141 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | 1900 + |
market segment | Storage + |
max cpu count | 1 + |
microarchitecture | Armv8.1 + |
name | Octeon TX CN8020 + |
series | CN80xx + |
smp max ways | 1 + |
supported memory type | DDR3/4-2100 + |
technology | CMOS + |
thread count | 2 + |
word size | 64 bit (8 octets, 16 nibbles) + |