| Edit Values | 
| Cavium CN3850-400 NSP | 
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| Designer | Cavium | 
| Manufacturer | TSMC | 
| Model Number | CN3850-400 NSP | 
| Part Number | CN3850-400BG1521-NSP | 
| Market | Networking | 
| Introduction | September 13, 2004 (announced) June 1, 2005 (launched) | 
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| Family | OCTEON | 
| Series | CN3800 | 
| Frequency | 400 MHz | 
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| ISA | MIPS64 (MIPS) | 
| Microarchitecture | cnMIPS | 
| Core Name | cnMIPS | 
| Process | 130 nm | 
| Technology | CMOS | 
| Word Size | 64 bit | 
| Cores | 12 | 
| Threads | 12 | 
| Max Memory | 16 GiB | 
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| Max SMP | 1-Way (Uniprocessor) | 
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| Package | FCBGA-1521 (BGA) |  
| Ball Count | 1521 |  
| Interconnect | BGA-1521 |  
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The CN3850-400 NSP is a 64-bit dodeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
 
[Edit/Modify Cache Info]
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Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a  CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in  kibibytes and  mebibytes.   
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| L1$ | 480 KiB 491,520 B  0.469 MiB 
   | | L1I$ | 384 KiB 393,216 B  0.375 MiB 
   | 12x32 KiB | 64-way set associative |   | 
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 | L1D$ | 96 KiB 98,304 B  0.0938 MiB 
   | 12x8 KiB | 64-way set associative | Write-through | 
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  |  | L2$ | 1 MiB 1,024 KiB  1,048,576 B  9.765625e-4 GiB 
   | |   |   | 1x1 MiB | 8-way set associative |   | 
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Memory controller
[Edit/Modify Memory Info]
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 Integrated Memory Controller 
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| Max Type | DDR2-800 | 
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 | Supports ECC | Yes | 
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 | Max Mem | 16 GiB | 
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 | Controllers | 1 | 
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 | Channels | 1 | 
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 | Width | 128 bit | 
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 | Max Bandwidth | 11.92 GiB/s 12,206.08 MiB/s  12.799 GB/s  12,799.003 MB/s  0.0116 TiB/s  0.0128 TB/s 
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 | Bandwidth | 
 Single 11.92 GiB/s 
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Expansions
Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
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 Hardware Accelerators 
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| Encryption | | Hardware Implementation | Yes | 
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 | Types | DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | 
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 | RegEx | | RegEx | Yes | 
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 | Features | 16 Engines | 
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 | Compression | | Compression | Yes | 
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 | Decompression | Yes | 
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Block diagram
Datasheet