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    CN3830-500 SCP  - Cavium    
                	
														| Edit Values | |||||||
| Cavium CN3830-500 SCP | |||||||
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| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN3830-500 SCP | ||||||
| Part Number | CN3830-500BG1521-SCP | ||||||
| Market | Networking | ||||||
| Introduction | September 13, 2004 (announced) June 1, 2005 (launched)  | ||||||
| General Specs | |||||||
| Family | OCTEON | ||||||
| Series | CN3800 | ||||||
| Frequency | 500 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Core Name | cnMIPS | ||||||
| Process | 130 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 4 | ||||||
| Threads | 4 | ||||||
| Max Memory | 16 GiB | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Packaging | |||||||
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The CN3830-500 SCP is a 64-bit quad-core MIPS secure network communication microprocessor (SNP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Expansions
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 Expansion Options 
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Networking
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 Networking 
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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 Hardware Accelerators 
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Block diagram
Datasheet
Facts about "CN3830-500 SCP  - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | CN3830-500 SCP - Cavium#package + | 
| base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + | 
| core count | 4 + | 
| core name | cnMIPS + | 
| designer | Cavium + | 
| family | OCTEON + | 
| first announced | September 13, 2004 + | 
| first launched | June 1, 2005 + | 
| full page name | cavium/octeon/cn3830-500bg1521-scp + | 
| has ecc memory support | true + | 
| has hardware accelerators for cryptography | true + | 
| has hardware accelerators for network quality of service processing | true + | 
| has hardware accelerators for tcp packet processing | true + | 
| instance of | microprocessor + | 
| isa | MIPS64 + | 
| isa family | MIPS + | 
| l1$ size | 160 KiB (163,840 B, 0.156 MiB) + | 
| l1d$ description | 64-way set associative + | 
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + | 
| l1i$ description | 64-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| ldate | June 1, 2005 + | 
| main image |    + | 
| manufacturer | TSMC + | 
| market segment | Networking + | 
| max cpu count | 1 + | 
| max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + | 
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + | 
| max memory channels | 1 + | 
| microarchitecture | cnMIPS + | 
| model number | CN3830-500 SCP + | 
| name | Cavium CN3830-500 SCP + | 
| package | FCBGA-1521 + | 
| part number | CN3830-500BG1521-SCP + | 
| process | 130 nm (0.13 μm, 1.3e-4 mm) + | 
| series | CN3800 + | 
| smp max ways | 1 + | 
| supported memory type | DDR2-800 + | 
| technology | CMOS + | 
| thread count | 4 + | 
| word size | 64 bit (8 octets, 16 nibbles) + | 
