Edit Values |
Cavium CN3630-400 EXP |
![octeon cn38xx.png](/w/images/e/e6/octeon_cn38xx.png) |
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Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3630-400 EXP |
Part Number | CN3630-400BG1521-EXP |
Market | Networking |
Introduction | August, 2005 (announced) August, 2005 (launched) |
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Family | OCTEON |
Series | CN3600 |
Frequency | 400 MHz |
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ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 4 |
Threads | 4 |
Max Memory | 16 GiB |
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Max SMP | 1-Way (Uniprocessor) |
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Power dissipation | 14 W |
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Package | FCBGA-1521 (BGA) |
Ball Count | 1521 |
Interconnect | BGA-1521 |
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The CN3630-400 EXP is a 64-bit quad-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 400 MHz and dissipates 14 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
![hierarchy icon.svg](/w/images/thumb/e/e4/hierarchy_icon.svg/75px-hierarchy_icon.svg.png) |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 160 KiB 163,840 B 0.156 MiB
| L1I$ | 128 KiB 131,072 B 0.125 MiB
| 4x32 KiB | 64-way set associative | |
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L1D$ | 32 KiB 32,768 B 0.0313 MiB
| 4x8 KiB | 64-way set associative | Write-through |
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| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB
| | | 1x512 KiB | 8-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
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Max Type | DDR2-800 |
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Supports ECC | Yes |
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Max Mem | 16 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 64 bit |
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Max Bandwidth | 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s
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Bandwidth |
Single 5.96 GiB/s
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Expansions
Networking
Hardware Accelerators
Block diagram
Datasheet