Edit Values |
Cavium CN3110-500 SCP |
![octeon cn31xx.png](/w/images/6/6d/octeon_cn31xx.png) |
|
Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3110-500 SCP |
Part Number | CN3110-500BG868-SCP |
Market | Embedded |
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) |
|
Family | OCTEON |
Series | CN3100 |
Frequency | 500 MHz |
|
ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
|
Max SMP | 1-Way (Uniprocessor) |
|
Package | HSBGA-868 (BGA) |
Ball Count | 868 |
Interconnect | BGA-868 |
|
The CN3110-500 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates a cnMIPS core, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
![hierarchy icon.svg](/w/images/thumb/e/e4/hierarchy_icon.svg/75px-hierarchy_icon.svg.png) |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
|
L1$ | 40 KiB 40,960 B 0.0391 MiB
| L1I$ | 32 KiB 32,768 B 0.0313 MiB
| 1x32 KiB | 4-way set associative | |
---|
L1D$ | 8 KiB 8,192 B 0.00781 MiB
| 1x8 KiB | 64-way set associative | Write-through |
---|
|
---|
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB
| | | 1x256 KiB | 8-way set associative | |
---|
|
---|
|
Memory controller
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
|
Max Type | DDR2-667 |
---|
Supports ECC | Yes |
---|
Max Mem | 4 GiB |
---|
Controllers | 1 |
---|
Channels | 1 |
---|
Width | 64 bit |
---|
Max Bandwidth | 4.97 GiB/s 5,089.28 MiB/s 5.336 GB/s 5,336.497 MB/s 0.00485 TiB/s 0.00534 TB/s
|
---|
Bandwidth |
Single 4.97 GiB/s
|
|
Optional low-latency controller for content-based processing and meta data
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
|
Max Type | DDR2-667 |
---|
Supports ECC | Yes |
---|
Max Mem | 2 GiB |
---|
Controllers | 1 |
---|
Channels | 1 |
---|
Width | 16 bit |
---|
Max Bandwidth | 1.24 GiB/s 1,269.76 MiB/s 1.331 GB/s 1,331.44 MB/s 0.00121 TiB/s 0.00133 TB/s
|
---|
Bandwidth |
Single 1.24 GiB/s
|
|
Expansions
Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
![hardware accel icon.svg](/w/images/thumb/b/b0/hardware_accel_icon.svg/75px-hardware_accel_icon.svg.png) |
Hardware Accelerators
|
Encryption | Hardware Implementation | Yes |
---|
Types | DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH |
---|
|
---|
|
Block diagram
Datasheet