Edit Values |
Cavium CN3010-400 SCP |
![cn3005-15.png](/w/images/3/32/cn3005-15.png) |
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Designer | Cavium |
Manufacturer | TSMC |
Model Number | CN3010-400 SCP |
Part Number | CN3010-400BG525-SCP |
Market | Embedded |
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) |
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Family | OCTEON |
Series | CN3000 |
Frequency | 400 MHz |
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ISA | MIPS64 (MIPS) |
Microarchitecture | cnMIPS |
Core Name | cnMIPS |
Process | 130 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 2 GiB |
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Max SMP | 1-Way (Uniprocessor) |
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Power dissipation | 3 W |
The CN3010-400 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in early 2006. This processor, which incorporates a single cnMIPS core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).
Cache
- Main article: cnMIPS § Cache
[Edit/Modify Cache Info]
![hierarchy icon.svg](/w/images/thumb/e/e4/hierarchy_icon.svg/75px-hierarchy_icon.svg.png) |
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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L1$ | 24 KiB 24,576 B 0.0234 MiB
| L1I$ | 16 KiB 16,384 B 0.0156 MiB
| 1x16 KiB | 2-way set associative | |
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L1D$ | 8 KiB 8,192 B 0.00781 MiB
| 1x8 KiB | 64-way set associative | Write-through |
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| L2$ | 128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB
| | | 1x128 KiB | 4-way set associative | |
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Memory controller
[Edit/Modify Memory Info]
![ram icons.svg](/w/images/thumb/a/af/ram_icons.svg/75px-ram_icons.svg.png) |
Integrated Memory Controller
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Max Type | DDR2-533 |
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Supports ECC | Yes |
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Max Mem | 2 GiB |
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Controllers | 1 |
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Channels | 1 |
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Width | 32 bit |
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Max Bandwidth | 1.986 GiB/s 2,033.664 MiB/s 2.132 GB/s 2,132.451 MB/s 0.00194 TiB/s 0.00213 TB/s
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Bandwidth |
Single 1.986 GiB/s
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Expansions
[Edit/Modify Expansions Info]
![ide icon.svg](/w/images/thumb/8/84/ide_icon.svg/75px-ide_icon.svg.png) |
Expansion Options
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PCI | Width | 32 bit |
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Clock | 66.66 MHz |
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Rate | 254.31 MiB/s |
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Features | host or slave |
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USB | Revision | 2.0 |
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Ports | 1 |
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Rate | 60 MB/s |
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Features | host / PHY |
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Networking
Hardware Accelerators
[Edit/Modify Accelerators Info]
![hardware accel icon.svg](/w/images/thumb/b/b0/hardware_accel_icon.svg/75px-hardware_accel_icon.svg.png) |
Hardware Accelerators
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Encryption | Hardware Implementation | Yes |
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Types | DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH |
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Block diagram
Datasheet