Edit Values |
Cortex-A72 µarch |
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Arch Type | CPU |
Designer | ARM Holdings |
Manufacturer | TSMC |
Introduction | April 23, 2015 |
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ISA | ARMv8 |
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Cortex-A72 (codename Maia) is the successor to the Cortex-A57, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A72, which implemented the ARMv8 ISA, is a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.
Compiler support
Compiler |
Arch-Specific |
Arch-Favorable
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Arm Compiler |
-mcpu=cortex-a72 |
-mtune=cortex-a72
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GCC |
-mcpu=cortex-a72 |
-mtune=cortex-a72
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LLVM |
-mcpu=cortex-a72 |
-mtune=cortex-a72
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If the Cortex-A72 is coupled with the Cortex-A53 or the Cortex-A35 in a big.LITTLE system, GCC also supports the following option:
Compiler |
Tune
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GCC |
-mtune=cortex-a72.cortex-a53
-mtune=cortex-a72.cortex-a35
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Architecture
Block Diagram
Memory Hierarchy
Die
- TSMC 20 nm process
- 100 mm² die size
- Quad-core ULP Cortex-A53
- Quad-core efficient Cortex-A53
- Dual-core High-performance Cortex-A72 + 1 MiB L2
- ~27.36 mm² per cluster
- ~ 9.60 mm² per core
- ~ 7.50 mm² for 1 MiB L2
Bibliography
- Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.