Semiconductor & Computer Engineering
From WikiChip
X-Gene 1 APM883204-X1 - AppliedMicro
| Edit Values | |
| APM883204-X1 | |
| General Info | |
| Designer | AppliedMicro |
| Manufacturer | TSMC |
| Model Number | APM883204-X1 |
| Market | Server |
| Introduction | October 28, 2011 (announced) 2012 (launched) |
| General Specs | |
| Family | X-Gene |
| Series | X-Gene 1 |
| Turbo Frequency | 2,400 MHz |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Storm |
| Core Name | Potenza |
| Process | 40 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 4 |
| Threads | 4 |
| Max Memory | 256 GiB |
| Electrical | |
| Vcore | 0.9 V |
| VI/O | 1.8 V, 2.5 V, 3.3 V |
| TDP | 45 W |
| Tjunction | 0 °C – 90 °C |
APM883204-X1 is a 64-bit quad-core ARM server microprocessor designed by AppliedMicro and introduced in 2012. Fabricated on TSMC 40 nm process based on the Storm microarchitecture, this processor has four custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.
Cache
- Main article: Storm § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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- 2x I2C
- 4x UARTs
- GPIOs
- 2x SPI
- 2x SDIO 3.0
- JTAG / Trace
Network
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Networking
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- Note: some ports are muxed
Block diagram
Documents
Facts about "X-Gene 1 APM883204-X1 - AppliedMicro"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | X-Gene 1 APM883204-X1 - AppliedMicro#pcie + |
| core count | 4 + |
| core name | Potenza + |
| core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
| designer | AppliedMicro + |
| family | X-Gene + |
| first announced | October 28, 2011 + |
| first launched | 2012 + |
| full page name | apm/x-gene/apm883204-x1 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.5 V (25 dV, 250 cV, 2,500 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| isa | ARMv8 + |
| isa family | ARM + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| ldate | 2012 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
| max memory | 262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) + |
| max memory bandwidth | 55.63 GiB/s (56,965.12 MiB/s, 59.732 GB/s, 59,732.258 MB/s, 0.0543 TiB/s, 0.0597 TB/s) + |
| max memory channels | 4 + |
| max sata ports | 6 + |
| max usb ports | 2 + |
| microarchitecture | Storm + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| model number | APM883204-X1 + |
| name | APM883204-X1 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + |
| series | X-Gene 1 + |
| supported memory type | DDR3-1866 + |
| tdp | 45 W (45,000 mW, 0.0603 hp, 0.045 kW) + |
| technology | CMOS + |
| thread count | 4 + |
| turbo frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |