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K6-2+/500ACZ - AMD
Edit Values | |
K6-2+/500ACZ | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | K6-2+/500ACZ |
Part Number | AMD-K6-2+/500ACZ |
Market | Mobile |
Introduction | April 18, 2000 (launched) |
Shop | Amazon |
General Specs | |
Family | K6-2+ |
Series | K6-2+ Mobile |
Frequency | 500 MHz |
Bus type | FSB |
Bus speed | 100 MHz |
Bus rate | 100 MT/s |
Clock multiplier | 5.0 |
CPUID | 5D4 |
Microarchitecture | |
Microarchitecture | K6-III |
Platform | Super 7 |
Core Family | 5 |
Core Model | 13 |
Core Stepping | 4, 5, 6, 7 |
Process | 0.18 µm |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Power dissipation | 12.6 W |
Vcore | 2.0 V ± 0.1 V |
VI/O | 3.3675 V ± 7% |
TDP | 16.0 W |
Tcase | 0 °C – 85 °C |
Packaging | |
Package | CPGA-321 |
Package Type | Ceramic Pin Grid Array |
Dimension | 49.5 mm × 49.5 mm |
Pitch | 2.54 mm |
Contacts | 321 |
Socket | Super Socket 7 |
K6-2+/500ACZ was a 32-bit x86 mobile microprocessor designed by AMD and introduced in early 2000. Based on the K6-III microarchitecture manufactured on a 0.18 µm process, this model operated at 500 MHz with a TDP of 16.0 W.
Contents
Cache
- Main article: K6-III § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This processor has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
References
- "Mobile AMD-K6®-2+ Processor Data Sheet", AMD Publ. #23446, Rev. B, June 1, 2000
Facts about "K6-2+/500ACZ - AMD"
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
bus rate | 100 MT/s (0.1 GT/s, 100,000 kT/s) + |
bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
bus type | FSB + |
clock multiplier | 5 + |
core count | 1 + |
core family | 5 + |
core model | 13 + |
core stepping | 4 +, 5 +, 6 + and 7 + |
core voltage | 2 V (20 dV, 200 cV, 2,000 mV) + |
core voltage tolerance | 0.1 V + |
cpuid | 5D4 + |
designer | AMD + |
family | K6-2+ + |
first launched | April 18, 2000 + |
full page name | amd/k6-2+/k6-2+-500acz + |
has feature | PowerNow! + |
instance of | microprocessor + |
io voltage | 3.368 V (33.675 dV, 336.75 cV, 3,367.5 mV) + |
io voltage tolerance | 7% + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + |
ldate | April 18, 2000 + |
manufacturer | AMD + |
market segment | Mobile + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
microarchitecture | K6-III + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | K6-2+/500ACZ + |
name | K6-2+/500ACZ + |
package | CPGA-321 + |
part number | AMD-K6-2+/500ACZ + |
platform | Super 7 + |
power dissipation | 12.6 W (12,600 mW, 0.0169 hp, 0.0126 kW) + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |
series | K6-2+ Mobile + |
smp max ways | 1 + |
socket | Super Socket 7 + |
tdp | 16 W (16,000 mW, 0.0215 hp, 0.016 kW) + |
technology | CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |