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List of results
- File:intel loihi many-core neural mesh.png + (07:17:50, 29 November 2017)
- 80286 - Microarchitectures - Intel + (23:24:45, 30 November 2017)
- Modified Pentium M - Microarchitectures - Intel + (23:26:02, 30 November 2017)
- 80386 - Microarchitectures - Intel + (23:34:10, 30 November 2017)
- 80486 - Microarchitectures - Intel + (23:34:32, 30 November 2017)
- P5 - Microarchitectures - Intel + (23:34:43, 30 November 2017)
- Airmont - Microarchitectures - Intel + (23:40:57, 30 November 2017)
- Saltwell - Microarchitectures - Intel + (23:42:05, 30 November 2017)
- Kittson - Microarchitectures - Intel + (23:54:39, 30 November 2017)
- Poulson - Microarchitectures - Intel + (23:54:52, 30 November 2017)
- Tukwila - Microarchitectures - Intel + (23:55:05, 30 November 2017)
- Montvale - Microarchitectures - Intel + (23:55:15, 30 November 2017)
- Montecito - Microarchitectures - Intel + (23:55:26, 30 November 2017)
- Chivano - Microarchitectures - Intel + (23:55:39, 30 November 2017)
- Madison 9M - Microarchitectures - Intel + (23:55:53, 30 November 2017)
- Madison - Microarchitectures - Intel + (23:56:06, 30 November 2017)
- McKinley - Microarchitectures - Intel + (23:56:23, 30 November 2017)
- K5 - Microarchitectures - AMD + (00:01:15, 1 December 2017)
- K6-2 - Microarchitectures - AMD + (00:01:47, 1 December 2017)
- K6-III - Microarchitectures - AMD + (00:02:01, 1 December 2017)
- HI + (11:03:44, 1 December 2017)
- File:intel interconnect 10 nm.jpg + (11:09:47, 7 December 2017)
- File:globalfoundries interconnect 7nm.jpg + (11:12:59, 7 December 2017)
- File:globalfoundries 7nm vs 14nm.jpg + (11:28:54, 7 December 2017)
- Cell Broadband Engine Architecture - Microarchitectures - IBM + (12:18:24, 7 December 2017)
- File:Cell processor.jpeg + (12:19:33, 7 December 2017)
- $longfn Identifier - mIRC + (21:16:59, 8 December 2017)
- $passivedcc identifier - mIRC + (01:51:07, 9 December 2017)
- /comopen Command - mIRC + (07:42:04, 9 December 2017)
- Massachusetts Institute of Technology + (01:57:16, 11 December 2017)
- University of California, Davis + (03:21:20, 11 December 2017)
- Category:entities + (03:39:23, 11 December 2017)
- Category:companies + (03:39:29, 11 December 2017)
- Category:universities + (03:39:46, 11 December 2017)
- Princeton University + (03:40:09, 11 December 2017)
- Category:instruction set architectures + (06:23:16, 11 December 2017)
- Category:MIPS + (06:23:23, 11 December 2017)
- Category:x86 + (06:25:26, 11 December 2017)
- Category:arm + (06:35:53, 11 December 2017)
- Category:risc-v + (06:48:01, 11 December 2017)
- Foundation - RISC-V + (08:01:00, 11 December 2017)
- File:gemini lake (front).png + (15:41:15, 11 December 2017)
- Category:microprocessor models by intel based on goldmont plus + (17:31:19, 11 December 2017)
- File:intel gemini lake chips.png + (18:18:32, 11 December 2017)
- File:intel pentium silver logo (2017).png + (19:03:32, 11 December 2017)
- File:intel pentium gold logo (2017).png + (19:11:22, 11 December 2017)
- File:intel celeron (2015).png + (19:42:33, 11 December 2017)
- Non-Standard Extensions - RISC-V + (05:40:56, 12 December 2017)
- File:risc-v base integer regsiters.svg + (06:34:00, 12 December 2017)
- Register + (07:02:43, 12 December 2017)
- Zero Register + (07:04:12, 12 December 2017)