| Edit Values |
| EPYC Embedded 3255 |
|
| Designer | AMD |
| Manufacturer | GlobalFoundries |
| Model Number | 3255 |
| Part Number | PE3255BGR88AF |
| Market | Server, Embedded |
| Shop | Amazon |
|
| Family | EPYC Embedded |
| Series | 3000 |
| Frequency | 2,500 MHz |
| Turbo Frequency | 3,100 MHz (8 cores) |
| Clock multiplier | 25 |
|
| ISA | x86-64 (x86) |
| Microarchitecture | Zen |
| Core Name | Snowy Owl |
| Core Family | 23 |
| Core Model | 1 |
| Process | 14 nm |
| Transistors | 9,600,000,000 |
| Technology | CMOS |
| Die | 213 mm² |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 16 |
| Max Memory | 512 GiB |
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| Max SMP | 1-Way (Uniprocessor) |
|
| TDP | 55 W |
| cTDP down | 30 W |
| Tjunction | -40 °C – 105 °C |
|
| Template:packages/amd/package sp4r2 |
EPYC Embedded 3255 is a 64-bit octa-core x86 embedded microprocessor for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.5 GHz with a TDP of 55 W and a turbo frequency of up to 3.1 GHz. This model supports a configurable TDP-down of 30 W and is distinguished from other EPYC Embedded 3000 Series processors by an industrial temperature range of -40 to 105 °C. The 3255 supports up to 512 GiB of dual-channel DDR4-2666 memory.
Cache
- Main article: Zen § Cache
[Edit/Modify Cache Info]
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Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
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| L1$ | 768 KiB 786,432 B 0.75 MiB
| | L1I$ | 512 KiB 524,288 B 0.5 MiB
| 8 × 64 KiB | 4-way set associative | |
|---|
| L1D$ | 256 KiB 262,144 B 0.25 MiB
| 8 × 32 KiB | 8-way set associative | write-back |
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| | L2$ | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB
| | | | 8 × 512 KiB | 8-way set associative | write-back |
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|
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| | L3$ | 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB
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Memory controller
[Edit/Modify Memory Info]
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Integrated Memory Controller
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| Max Type | DDR4-2666 |
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| Supports ECC | Yes |
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| Max Mem | 512 GiB |
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| Controllers | 2 |
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| Channels | 2 |
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| Max Bandwidth | 39.74 GiB/s 40,693.76 MiB/s 42.671 GB/s 42,670.5 MB/s 0.0388 TiB/s 0.0427 TB/s
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|---|
| Bandwidth |
Single 19.87 GiB/s Double 39.74 GiB/s
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|
| [Edit] Official AMD Supported Memory Configurations
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| Quad Channel |
Single Rank |
1 DIMM per channel |
4 of 8 |
DDR4-2666
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| 2 DIMMs per channel |
8 of 8 |
DDR4-2133
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| Dual Rank |
1 DIMM per channel |
4 of 8 |
DDR4-2400
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| 2 DIMMs per channel |
8 of 8 |
DDR4-1866
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Expansions
The EPYC Embedded 3255 supports up to 32 PCIe Gen 3 (8 GT/s) lanes. Some of these lanes can be configured as SATA 3 (6 Gb/s) and 10 Gigabit Ethernet ports. Up to 8 SATA ports and 4 GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: EMMC, eSPI, GPIO, I2C, LPC, SMBus, SPI, UART.
[Edit/Modify Expansions Info]
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Expansion Options |
| PCIe | Revision: 3.0 | | Max Lanes: 32 | | Configuration: x16, x8, x4, x2 |
| USB | Revision: 3.1 | | Max Ports: 4 |
| SATA | Revision: 3.0 | | Max Ports: 8 |
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Features
References