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From WikiChip
Cortex-A32 - Microarchitectures - ARM
< arm holdings
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
| Edit Values | |
| Cortex-A32 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | February 23, 2016 |
| Pipeline | |
| Stages | 8 |
| Instructions | |
| ISA | ARMv8 AArch32 |
| Extensions | NEON (optional), Cryptography (optional) |
| Cache | |
| L1I Cache | 8k-64k |
| L1D Cache | 8k-64k |
| L2 Cache | 128KB-1MB |
| Succession | |
Cortex-A32 (codename Minerva) is the successor to the Cortex-A35, an ultra-low power ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
Architecture[edit]
Key changes from Cortex-A5[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/cortex-a32&oldid=96579"
Hidden category:
Facts about "Cortex-A32 - Microarchitectures - ARM"
| codename | Cortex-A32 + |
| designer | ARM Holdings + |
| first launched | February 23, 2016 + |
| full page name | arm holdings/microarchitectures/cortex-a32 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 AArch32 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A32 + |
| pipeline stages | 8 + |