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From WikiChip
arm holdings/microarchitectures/neoverse n2
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/neoverse_n2&oldid=96450"
Facts about "Neoverse N2 - Microarchitectures - ARM"
| codename | Neoverse N2 + |
| core count | 4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 + |
| designer | ARM Holdings + |
| first launched | September 22, 2020 + |
| full page name | arm holdings/microarchitectures/neoverse n2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv9.0-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Neoverse N2 + |
| pipeline stages | 13 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + |