A scaling booster is an enhancement made to a process node beyond classical scaling vectors in order to allow Moore's Law device scaling to continue or accelerate.
Overview
As process nodes continues to shrink, classical scaling vectors (e.g., gate pitch) becomes increasingly challenging. There are multiple reasons for this including electrostatics in the FEOL, RC delays in the BEOL, as well as general routing challenges. Scaling boosters have been introduced in order to aid traditional scaling vectors through various modifications and enhancements. Scaling boosters may be part of the process technology flow itself or as part of the standard library as part of the design-technology co-optimization (DTCO). By combining scaling boosters with slightly less aggressive classical scaling vectors, a process node can achieve similar transistors density while keeping the process cost in check.
Boosters
Track Reduction
Self-Aligned Contacts (SAC)
- Main article: self-aligned contact (SAC)
The node continued to shrink the various features, the landing area for the gate contacts shrunk to a point where decreasing the pitch any further would result in uneconomical yield loss. Self-aligned contact (SAC) is a process enhancement technique that loosens up the alignment tolerances associated with the landing area of the gate contacts, thereby allowing the contacted gate pitch to shrink further while improving the yield by preventing yield loss due to the contact shorting the gate.
Self-Aligned Vias (SAV)
Single Diffusion Break (SDB)
Mixed Diffusion Break (MDB)
Contact Over Active Gate (COAG)
Buried Power Rail (BPR)
SuperVia
Fully Self Aligned Via (FSAV)
Self-Aligned Block (SAB)
