Documentation for this module may be created at Module:node/doc

local p = {}
local origArgs

function arg(name)
	return origArgs[name]
end

function p.node (frame)
    if frame == mw.getCurrentFrame() then
        origArgs = frame:getParent().args
    else
        origArgs = frame.args
    end
    
    if true then 
    return '@' .. arg('5 nm') .. '@'
	end

    if arg('5 nm') then
    	return '' ..
'<table class="wikitable" style="text-align: center;">' ..
'<tr><th colspan="2">&nbsp;</th><th colspan="2">[[Intel]]</th><th colspan="2">[[TSMC]]</th><th colspan="2">[[Samsung]]</th></tr>' ..
'<tr><th colspan="2">Process</th><td colspan="2">P1278 (CPU), P1279 (SoC)</td><td colspan="2">N5, N5P</td><td colspan="2">5LPP, 4LPP</td></tr>' ..
'<tr><th colspan="2">Production</th><td colspan="2">2023</td><td colspan="2">Q1\'2020</td><td colspan="2">2020</td></tr>' ..
'<tr><th rowspan="2">Litho</th><th>Lithography</th><td colspan="6">[[EUV]]</td></tr>' ..
'<tr><th>Immersion<br>Exposure</th><td colspan="2"></td><td colspan="2">SE (EUV)<br>DP (193i)</td><td colspan="2">SE (EUV)<br>DP (193i)</td></tr>' ..
'<tr><th rowspan="2">[[Wafer]]</th><th>Type</th><td colspan="6">Bulk</td></tr>' ..
'<tr><th>Size</th><td colspan="6">[[wafer size|300 mm]]</td></tr>' ..
'<tr><th rowspan="2">xTor</th><th>Type</th><td colspan="2"></td><td colspan="2">[[FinFET]]</td><td colspan="2">[[FinFET]]</td></tr>' ..
'<tr><th>Voltage</th><td colspan="2"></td><td colspan="2"></td><td colspan="2"></td></tr>' ..
'<tr><th colspan="2">&nbsp;</th><th>Value</th><th>[[7 nm]] Δ</th><th>Value</th><th>[[7 nm]] Δ</th><th>Value</th><th>[[7 nm]] Δ</th></tr>' ..
'<tr><th rowspan="3">Fin</th><th>Pitch</th><td></td><td></td><td></td><td></td><td>27 nm</td><td>1.0x</td></tr>' ..
'<tr><th>Width</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th>Height</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th colspan="2">Gate Length (L<sub>g</sub>)</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th colspan="2">Contacted Gate Pitch (CPP)</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th colspan="2">Minimum Metal Pitch (MMP)</th><td></td><td></td><td></td><td></td><td>36 nm</td><td>1.0x</td></tr>' ..
'<tr><th rowspan="3">[[SRAM]]</th><th>High-Perf (HP)</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'<tr><th>High-Density (HD)</th><td></td><td></td><td></td><td></td><td>0.0260 µm²</td><td>1.0x</td></tr>' ..
'<tr><th>Low-Voltage (LV)</th><td></td><td></td><td></td><td></td><td></td><td></td></tr>' ..
'</table>'
	end
    
end


return p