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General Info

Microarchitecture

APM883208-X2 is a 64-bit octa-core ARM server microprocessor designed by AppliedMicro and introduced in 2014. Fabricated on TSMC 28 nm process based on the Shadowcat microarchitecture, this processor has eight custom ARMv8 cores operating at up to 2.4 GHz and supporting up to 256 GiB of dual-channel DDR3-1866 memory.

Cache

Main article: Shadowcat § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative Write-through with write-combine L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB     L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     1x4 MiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1866 Supports ECC Yes Max Mem 256 GiB Controllers 1 Channels 2 Max Bandwidth 27.82 GiB/s 28,487.68 MiB/s 29.871 GB/s 29,871.498 MB/s 0.0272 TiB/s 0.0299 TB/s Bandwidth Single 13.91 GiB/s Double 27.82 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 17 Configuration: 1x16+x1, 2x8+x1 USB Revision: 2.0 Max Ports: 2 SATA Revision: 3.0 Max Ports: 6

• 2x I2C
• 4x UARTs
• GPIOs
• 2x SPI
• 2x SDIO 3.0
• JTAG / Trace

Network

[Edit/Modify Network Info]

	Networking
	MII RGMII Yes (Ports: 4) SGMII Yes (Ports: 1)

• Note: some ports are muxed