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Hi1620
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	Hi1620
Market	Server
Introduction	September, 2018 (announced) September, 2018 (launched)
General Specs
Family	Hi16xx
Frequency	3,000 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Ares
Core Name	Ares
Technology	CMOS
Word Size	64 bit
Cores	48
Threads	48
Max Memory	512 GiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)

Hi1620 is a planned octatetraconta-core 64-bit ARM server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by TSMC on a ? nm process, this chip incorporates 48 Ares cores operating at 3 GHz. The Hi1620 supports up to 512 GiB of quad-channel DDR4-2400 memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cortex-A72 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 3.75 MiB 3,840 KiB 3,932,160 B L1I$ 2.25 MiB 2,304 KiB 2,359,296 B 48x48 KiB 8-way set associative   L1D$ 1.5 MiB 1,536 KiB 1,572,864 B 48x32 KiB 8-way set associative   L2$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     48x256 KiB 8-way set associative   L3$ 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB     48x1 MiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2400 Supports ECC Yes Max Mem 512 GiB Controllers 1 Channels 4 Width 64 bit Max Bandwidth 71.53 GiB/s 73,246.72 MiB/s 76.805 GB/s 76,804.753 MB/s 0.0699 TiB/s 0.0768 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 16 Configuration: 2x8

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension

Utilizing devices

• HiSilicon D06

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