Edit Values
Tremont µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2018/2019
Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Instructions
ISA	x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cores
Core Names	Gemini Lake
Succession
Goldmont Plus

Tremont is Intel's successor to Goldmont Plus, an ultra-low power microarchitecture for low-power devices and microservers.

Codenames

This section is empty; you can help add the missing info by editing this page.

Brands

This section is empty; you can help add the missing info by editing this page.

Release Dates

This section is empty; you can help add the missing info by editing this page.

Technology

This section is empty; you can help add the missing info by editing this page.

Architecture

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont Plus

This section is empty; you can help add the missing info by editing this page.

New instructions

Termont introduced a number of new instructions:

• CLWB - Force cache line write-back without flush
• ENCLV - SGX oversubscription instructions
• CLDEMOTE - Cache line demote instruction
• SSE_GFNI - SSE-based Galois Field New Instructions
• Direct store instructions: MOVDIRI, MOVDIR64B
• User wait instructions: TPAUSE, UMONITOR, UMWAIT
• Split Lock Detection - detection and cause an exception for split locks